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author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 19:43:33 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-18 19:43:33 +0000 |
commit | 783893a893aab84ad6bc838be2dbb162093c9bcd (patch) | |
tree | afd8f87903ed651f6df9d5dcff16ee0851d5f3d8 | |
parent | f1e3f77507caf9dc063cd62d98588f964b5b30fe (diff) | |
download | bcm5719-llvm-783893a893aab84ad6bc838be2dbb162093c9bcd.tar.gz bcm5719-llvm-783893a893aab84ad6bc838be2dbb162093c9bcd.zip |
R600: Add a SubtargetFeatture for disabling the ifcvt pass.
This is useful when writing test cases for the AMDIL structurizer.
llvm-svn: 195029
-rw-r--r-- | llvm/lib/Target/R600/AMDGPU.td | 5 | ||||
-rw-r--r-- | llvm/lib/Target/R600/AMDGPUSubtarget.cpp | 5 | ||||
-rw-r--r-- | llvm/lib/Target/R600/AMDGPUSubtarget.h | 2 | ||||
-rw-r--r-- | llvm/lib/Target/R600/AMDGPUTargetMachine.cpp | 3 |
4 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/AMDGPU.td b/llvm/lib/Target/R600/AMDGPU.td index e9304c22612..37ff6b143a0 100644 --- a/llvm/lib/Target/R600/AMDGPU.td +++ b/llvm/lib/Target/R600/AMDGPU.td @@ -28,6 +28,11 @@ def FeatureIRStructurizer : SubtargetFeature <"enable-irstructurizer", // Target features +def FeatureIfCvt : SubtargetFeature <"disable-ifcvt", + "EnableIfCvt", + "false", + "Disable the if conversion pass">; + def FeatureFP64 : SubtargetFeature<"fp64", "FP64", "true", diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp index 1e21c8e8b5c..4e97e6e83bb 100644 --- a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp @@ -37,6 +37,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : FP64 = false; CaymanISA = false; EnableIRStructurizer = false; + EnableIfCvt = true; ParseSubtargetFeatures(GPU, FS); DevName = GPU; } @@ -70,6 +71,10 @@ AMDGPUSubtarget::IsIRStructurizerEnabled() const { return EnableIRStructurizer; } bool +AMDGPUSubtarget::isIfCvtEnabled() const { + return EnableIfCvt; +} +bool AMDGPUSubtarget::isTargetELF() const { return false; } diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.h b/llvm/lib/Target/R600/AMDGPUSubtarget.h index c08cd6a6b85..4288d275c99 100644 --- a/llvm/lib/Target/R600/AMDGPUSubtarget.h +++ b/llvm/lib/Target/R600/AMDGPUSubtarget.h @@ -50,6 +50,7 @@ private: bool FP64; bool CaymanISA; bool EnableIRStructurizer; + bool EnableIfCvt; InstrItineraryData InstrItins; @@ -66,6 +67,7 @@ public: bool hasHWFP64() const; bool hasCaymanISA() const; bool IsIRStructurizerEnabled() const; + bool isIfCvtEnabled() const; virtual bool enableMachineScheduler() const { return getGeneration() <= NORTHERN_ISLANDS; diff --git a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp index b19277d97be..9186c9df3ab 100644 --- a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -169,7 +169,8 @@ bool AMDGPUPassConfig::addPreSched2() { if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) addPass(createR600EmitClauseMarkers(*TM)); - addPass(&IfConverterID); + if (ST.isIfCvtEnabled()) + addPass(&IfConverterID); if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) addPass(createR600ClauseMergePass(*TM)); return false; |