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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-16 12:15:31 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-16 12:15:31 +0000 |
| commit | 780b3ca775852acacc4313e8d7ff9238184d7df2 (patch) | |
| tree | c570a5324d6cd202bbebeae2833c282dab21633e | |
| parent | ca72239534c4801577d372c03e40c3d59a9134f7 (diff) | |
| download | bcm5719-llvm-780b3ca775852acacc4313e8d7ff9238184d7df2.tar.gz bcm5719-llvm-780b3ca775852acacc4313e8d7ff9238184d7df2.zip | |
[X86] Add computeKnownBits tests for funnel shift intrinsics
llvm-svn: 349297
| -rw-r--r-- | llvm/test/CodeGen/X86/known-bits.ll | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/known-bits.ll b/llvm/test/CodeGen/X86/known-bits.ll index 2ff0939b3e7..3f7e127c072 100644 --- a/llvm/test/CodeGen/X86/known-bits.ll +++ b/llvm/test/CodeGen/X86/known-bits.ll @@ -298,3 +298,46 @@ declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone + +define i32 @knownbits_fshl(i32 %a0) nounwind { +; X32-LABEL: knownbits_fshl: +; X32: # %bb.0: +; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X32-NEXT: movl $-1, %eax +; X32-NEXT: shrdl $27, %ecx, %eax +; X32-NEXT: andl $3, %eax +; X32-NEXT: retl +; +; X64-LABEL: knownbits_fshl: +; X64: # %bb.0: +; X64-NEXT: movl $-1, %eax +; X64-NEXT: shrdl $27, %edi, %eax +; X64-NEXT: andl $3, %eax +; X64-NEXT: retq + %1 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 -1, i32 5) + %2 = and i32 %1, 3 + ret i32 %2 +} + +define i32 @knownbits_fshr(i32 %a0) nounwind { +; X32-LABEL: knownbits_fshr: +; X32: # %bb.0: +; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X32-NEXT: movl $-1, %eax +; X32-NEXT: shrdl $5, %ecx, %eax +; X32-NEXT: andl $3, %eax +; X32-NEXT: retl +; +; X64-LABEL: knownbits_fshr: +; X64: # %bb.0: +; X64-NEXT: movl $-1, %eax +; X64-NEXT: shrdl $5, %edi, %eax +; X64-NEXT: andl $3, %eax +; X64-NEXT: retq + %1 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 -1, i32 5) + %2 = and i32 %1, 3 + ret i32 %2 +} + +declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone +declare i32 @llvm.fshr.i32(i32, i32, i32) nounwind readnone |
