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authorDan Gohman <gohman@apple.com>2010-05-06 05:08:57 +0000
committerDan Gohman <gohman@apple.com>2010-05-06 05:08:57 +0000
commit77c71811f5a8e5aebba075a3b0d56c8f37141dc0 (patch)
treeac16a7eb5b47be74b0f4c9c9d6ba8250e02daf01
parenta77a72734cf8735c9b2b81e41e7468369fec626e (diff)
downloadbcm5719-llvm-77c71811f5a8e5aebba075a3b0d56c8f37141dc0.tar.gz
bcm5719-llvm-77c71811f5a8e5aebba075a3b0d56c8f37141dc0.zip
Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.
llvm-svn: 103163
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 76e5bbba34e..0cf85e86afb 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -540,6 +540,8 @@ bool
ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
+ SrcSubIdx = DstSubIdx = 0; // No sub-registers.
+
switch (MI.getOpcode()) {
default: break;
case ARM::VMOVS:
@@ -548,8 +550,6 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
case ARM::VMOVQ: {
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
case ARM::MOVr:
@@ -564,8 +564,6 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
"Invalid ARM MOV instruction");
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
- SrcSubIdx = MI.getOperand(1).getSubReg();
- DstSubIdx = MI.getOperand(0).getSubReg();
return true;
}
}
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