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author | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 00:32:06 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 00:32:06 +0000 |
commit | 76b561dd709844183931d83c447c48772a4874fc (patch) | |
tree | 8452eacb02a00a509c09a32104b2169f8471494c | |
parent | 7c701e7d8659b79c011760222b3cd16cddffd06b (diff) | |
download | bcm5719-llvm-76b561dd709844183931d83c447c48772a4874fc.tar.gz bcm5719-llvm-76b561dd709844183931d83c447c48772a4874fc.zip |
Fix my brain cramp by inverting the assertion condition.
llvm-svn: 76131
-rw-r--r-- | llvm/lib/CodeGen/VirtRegRewriter.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/VirtRegRewriter.cpp b/llvm/lib/CodeGen/VirtRegRewriter.cpp index 2213c65f343..abaa8bd212e 100644 --- a/llvm/lib/CodeGen/VirtRegRewriter.cpp +++ b/llvm/lib/CodeGen/VirtRegRewriter.cpp @@ -491,13 +491,11 @@ static void ReMaterialize(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI, VirtRegMap &VRM) { MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); -#if 0 #ifndef NDEBUG const TargetInstrDesc &TID = ReMatDefMI->getDesc(); - assert(TID.getNumDefs() != 1 && + assert(TID.getNumDefs() == 1 && "Don't know how to remat instructions that define > 1 values!"); #endif -#endif TII->reMaterialize(MBB, MII, DestReg, ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI); MachineInstr *NewMI = prior(MII); |