diff options
| author | Jim Grosbach <grosbach@apple.com> | 2011-11-15 22:27:54 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-15 22:27:54 +0000 |
| commit | 75fb4abcdc5e216d5b107c3b66dc56aad8830306 (patch) | |
| tree | 53101bcbda8dfb9ad90f1606052b5cbd31576a1b | |
| parent | 4bf80d5544a58b8b149f3a3e501c6560a6784097 (diff) | |
| download | bcm5719-llvm-75fb4abcdc5e216d5b107c3b66dc56aad8830306.tar.gz bcm5719-llvm-75fb4abcdc5e216d5b107c3b66dc56aad8830306.zip | |
ARM assembly parsing two operand forms for shift instructions.
llvm-svn: 144713
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 10 | ||||
| -rw-r--r-- | llvm/test/MC/ARM/basic-arm-instructions.s | 8 |
2 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index c7772875c36..da3a1be71ba 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -5023,6 +5023,16 @@ def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; +// shifter instructions also support a two-operand form. +def : ARMInstAlias<"asr${s}${p} $Rm, $imm", + (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"lsr${s}${p} $Rm, $imm", + (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"lsl${s}${p} $Rm, $imm", + (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; +def : ARMInstAlias<"ror${s}${p} $Rm, $imm", + (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; + // 'mul' instruction can be specified with only two operands. def : ARMInstAlias<"mul${s}${p} $Rn, $Rm", diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s index 2217c8aaae5..da216fa335a 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions.s +++ b/llvm/test/MC/ARM/basic-arm-instructions.s @@ -262,10 +262,12 @@ Lforward: asr r2, r4, #32 asr r2, r4, #2 asr r2, r4, #0 + asr r4, #2 @ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1] @ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1] @ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: asr r4, r4, #2 @ encoding: [0x44,0x41,0xa0,0xe1] @------------------------------------------------------------------------------ @@ -794,10 +796,12 @@ Lforward: lsl r2, r4, #31 lsl r2, r4, #1 lsl r2, r4, #0 + lsl r4, #1 @ CHECK: lsl r2, r4, #31 @ encoding: [0x84,0x2f,0xa0,0xe1] @ CHECK: lsl r2, r4, #1 @ encoding: [0x84,0x20,0xa0,0xe1] @ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: lsl r4, r4, #1 @ encoding: [0x84,0x40,0xa0,0xe1] @------------------------------------------------------------------------------ @@ -806,10 +810,12 @@ Lforward: lsr r2, r4, #32 lsr r2, r4, #2 lsr r2, r4, #0 + lsr r4, #2 @ CHECK: lsr r2, r4, #32 @ encoding: [0x24,0x20,0xa0,0xe1] @ CHECK: lsr r2, r4, #2 @ encoding: [0x24,0x21,0xa0,0xe1] @ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: lsr r4, r4, #2 @ encoding: [0x24,0x41,0xa0,0xe1] @------------------------------------------------------------------------------ @@ -1346,10 +1352,12 @@ Lforward: ror r2, r4, #31 ror r2, r4, #1 ror r2, r4, #0 + ror r4, #1 @ CHECK: ror r2, r4, #31 @ encoding: [0xe4,0x2f,0xa0,0xe1] @ CHECK: ror r2, r4, #1 @ encoding: [0xe4,0x20,0xa0,0xe1] @ CHECK: mov r2, r4 @ encoding: [0x04,0x20,0xa0,0xe1] +@ CHECK: ror r4, r4, #1 @ encoding: [0xe4,0x40,0xa0,0xe1] @------------------------------------------------------------------------------ |
