summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPuyan Lotfi <puyan@puyan.org>2019-09-01 00:45:28 +0000
committerPuyan Lotfi <puyan@puyan.org>2019-09-01 00:45:28 +0000
commit75a8a212d4e48dd7a8a98ab174b207c1f8bc70a7 (patch)
treeae261d0d1b67001194a82facaf4f220c31c1b249
parent1594605416f12bf2b53e7294ac154ea451d6458f (diff)
downloadbcm5719-llvm-75a8a212d4e48dd7a8a98ab174b207c1f8bc70a7.tar.gz
bcm5719-llvm-75a8a212d4e48dd7a8a98ab174b207c1f8bc70a7.zip
[GlobalISel][NFC] Regression test cases for aarch64 legalizer (s128 sext+icmp).
There were legalizer asserts in aarch64 globalisel (in debug mode) with s128 sext+icmp before r367060 and r366943 landed. These are just a couple reduced mir and ir regression tests that came from a build where these were encountered. llvm-svn: 370602
-rw-r--r--llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll9
-rw-r--r--llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir23
2 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll
new file mode 100644
index 00000000000..aff5245d905
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.ll
@@ -0,0 +1,9 @@
+; RUN: llc -O0 --global-isel=1 %s -o - -verify-machineinstrs
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define i1 @foo(i64) {
+ %a = sext i64 %0 to i128
+ %b = icmp sle i128 %a, 0
+ ret i1 %b
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir
new file mode 100644
index 00000000000..b1ccf02a572
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-128.mir
@@ -0,0 +1,23 @@
+# RUN: llc -o - --global-isel=1 -verify-machineinstrs -run-pass=legalizer -x mir %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-unknown-linux-gnu"
+ define i1 @foo(i64) {
+ %a = sext i64 %0 to i128
+ %b = icmp sle i128 %a, 0
+ ret i1 %b
+ }
+...
+---
+name: foo
+body: |
+ bb.1 (%ir-block.1):
+ liveins: $x0
+ %namedVReg4352:_(s64) = COPY $x0
+ %namedVReg1356:_(s128) = G_CONSTANT i128 0
+ %namedVReg1355:_(s128) = G_SEXT %namedVReg4352(s64)
+ %namedVReg1354:_(s1) = G_ICMP intpred(sle), %namedVReg1355(s128), %namedVReg1356
+ %namedVReg1353:_(s32) = G_SEXT %namedVReg1354(s1)
+ $w0 = COPY %namedVReg1353(s32)
+ RET_ReallyLR implicit $w0
+...
OpenPOWER on IntegriCloud