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| author | Eli Friedman <eli.friedman@gmail.com> | 2010-08-02 00:18:19 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2010-08-02 00:18:19 +0000 |
| commit | 7595ce05a2aa7e9fb378215ec5daf8cc056c71d8 (patch) | |
| tree | a7728519a66d7a14dc707f1fe5a36041b38e0928 | |
| parent | b1af605e58fc2884d512696e2cae7e513d3e07fb (diff) | |
| download | bcm5719-llvm-7595ce05a2aa7e9fb378215ec5daf8cc056c71d8.tar.gz bcm5719-llvm-7595ce05a2aa7e9fb378215ec5daf8cc056c71d8.zip | |
PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
llvm-svn: 109998
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vec_constants.ll | 18 |
2 files changed, 14 insertions, 10 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d47d989b34c..33d14412848 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3942,17 +3942,17 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, } // t = vsplti c, result = vsldoi t, t, 1 - if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { + if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 2 - if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { + if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 3 - if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { + if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); } diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll index 32c6f4809cb..399f19f8d2e 100644 --- a/llvm/test/CodeGen/PowerPC/vec_constants.ll +++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI -define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { +define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] store <4 x i32> %tmp4, <4 x i32>* %P1 @@ -15,26 +15,30 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { ret void } -define <4 x i32> @test_30() { +define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > } -define <4 x i32> @test_29() { +define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > } -define <8 x i16> @test_n30() { +define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > } -define <16 x i8> @test_n104() { +define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > } -define <4 x i32> @test_vsldoi() { +define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > } -define <4 x i32> @test_rol() { +define <8 x i16> @test_vsldoi_65023() nounwind { + ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > +} + +define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > } |
