diff options
| author | Bill Wendling <isanbard@gmail.com> | 2008-07-20 02:32:23 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2008-07-20 02:32:23 +0000 |
| commit | 75840e6435dcc061d83c8dfda1d71696207589cd (patch) | |
| tree | 2bf92fbb9d1fb74b92784d4f4c851c3c1d49d5aa | |
| parent | 1071bfb17d2f0ac1ccb9aa6744f6e746fcf99e1e (diff) | |
| download | bcm5719-llvm-75840e6435dcc061d83c8dfda1d71696207589cd.tar.gz bcm5719-llvm-75840e6435dcc061d83c8dfda1d71696207589cd.zip | |
Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts
into v4i16 vectors.
llvm-svn: 53807
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/mmx-pinsrw.ll | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8bfa574fb79..85788ef90c7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -604,6 +604,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); + + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); } if (Subtarget->hasSSE1()) { diff --git a/llvm/test/CodeGen/X86/mmx-pinsrw.ll b/llvm/test/CodeGen/X86/mmx-pinsrw.ll new file mode 100644 index 00000000000..f1d04fa46ca --- /dev/null +++ b/llvm/test/CodeGen/X86/mmx-pinsrw.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep pinsrw | count 1 +; PR2562 + +external global i16 ; <i16*>:0 [#uses=1] +external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2] + +declare void @abort() + +define void @""() { + load i16* @0 ; <i16>:1 [#uses=1] + load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1] + insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1] + store <4 x i16> %3, <4 x i16>* @1 + ret void +} |
