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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-11-16 19:55:12 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-11-16 19:55:12 +0000 |
| commit | 7583f689547faa4361512272fd73acb44a71fabf (patch) | |
| tree | 79fc153b12ef1426be83aee7c02deb73695bf77b | |
| parent | 43b3bad58beca5081d2a536eb545023da70940e2 (diff) | |
| download | bcm5719-llvm-7583f689547faa4361512272fd73acb44a71fabf.tar.gz bcm5719-llvm-7583f689547faa4361512272fd73acb44a71fabf.zip | |
Print out the register class of the current interval.
llvm-svn: 119374
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocLinearScan.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/RegAllocLinearScan.cpp b/llvm/lib/CodeGen/RegAllocLinearScan.cpp index 81b9070af29..c0720fe9d13 100644 --- a/llvm/lib/CodeGen/RegAllocLinearScan.cpp +++ b/llvm/lib/CodeGen/RegAllocLinearScan.cpp @@ -954,10 +954,11 @@ namespace { /// assignRegOrStackSlotAtInterval - assign a register if one is available, or /// spill. void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) { - DEBUG(dbgs() << "\tallocating current interval: "); + const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); + DEBUG(dbgs() << "\tallocating current interval from " + << RC->getName() << ": "); // This is an implicitly defined live interval, just assign any register. - const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); if (cur->empty()) { unsigned physReg = vrm_->getRegAllocPref(cur->reg); if (!physReg) |
