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| author | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 17:03:12 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-25 17:03:12 +0000 |
| commit | 757ca6977085566766c6f0a9a161a40478bd90e8 (patch) | |
| tree | 72e45de22729304aab227e6f0cf36fd644c2b1ce | |
| parent | 1102c9ae58ecafa26dc088d75abee3591dede94e (diff) | |
| download | bcm5719-llvm-757ca6977085566766c6f0a9a161a40478bd90e8.tar.gz bcm5719-llvm-757ca6977085566766c6f0a9a161a40478bd90e8.zip | |
Also need to handle invalid imod values for CPS2p.
rdar://problem/9186136
llvm-svn: 128283
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt | 4 |
2 files changed, 15 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index b839a02d6a1..ff19a385cf4 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2965,8 +2965,10 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // opcodes which match the same real instruction. This is needed since there's // no current handling of optional arguments. Fix here when a better handling // of optional arguments is implemented. - if (Opcode == ARM::CPS3p) { - // Let's reject impossible imod values by returning false. + if (Opcode == ARM::CPS3p) { // M = 1 + // Let's reject these impossible imod values by returning false: + // 1. (imod=0b01) + // // AsmPrinter cannot handle imod=0b00, plus (imod=0b00,M=1,iflags!=0) is an // invalid combination, so we just check for imod=0b00 here. if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1) @@ -2977,13 +2979,18 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, NumOpsAdded = 3; return true; } - if (Opcode == ARM::CPS2p) { + if (Opcode == ARM::CPS2p) { // mode = 0, M = 0 + // Let's reject these impossible imod values by returning false: + // 1. (imod=0b00,M=0) + // 2. (imod=0b01) + if (slice(insn, 19, 18) == 0 || slice(insn, 19, 18) == 1) + return false; MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 18))); // imod MI.addOperand(MCOperand::CreateImm(slice(insn, 8, 6))); // iflags NumOpsAdded = 2; return true; } - if (Opcode == ARM::CPS1p) { + if (Opcode == ARM::CPS1p) { // imod = 0, iflags = 0, M = 1 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0))); // mode NumOpsAdded = 1; return true; diff --git a/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt new file mode 100644 index 00000000000..10748e9b126 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# invalid imod value (0b01) +0xc0 0x67 0x4 0xf1 |
