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| author | Eric Christopher <echristo@gmail.com> | 2014-07-18 20:35:49 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2014-07-18 20:35:49 +0000 |
| commit | 754d54fcf8ccf972d0785596aaf83aed4a1edf7f (patch) | |
| tree | c4ec9c6ba8780c9f7b9d199d11ea89f2305aa4a7 | |
| parent | 76774a57d8aee0066cb58b825d79aea056eb67b1 (diff) | |
| download | bcm5719-llvm-754d54fcf8ccf972d0785596aaf83aed4a1edf7f.tar.gz bcm5719-llvm-754d54fcf8ccf972d0785596aaf83aed4a1edf7f.zip | |
Fix a couple of formatting and style issues.
llvm-svn: 213409
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.cpp | 34 |
1 files changed, 14 insertions, 20 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index d6da6c6b172..1db89c65a9a 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -94,10 +94,10 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, return (BT == BT_None) || (BT == BT_Indirect); } -void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, DebugLoc DL, - const SmallVectorImpl<MachineOperand>& Cond) - const { +void +MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + DebugLoc DL, + const SmallVectorImpl<MachineOperand> &Cond) const { unsigned Opc = Cond[0].getImm(); const MCInstrDesc &MCID = get(Opc); MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); @@ -113,11 +113,9 @@ void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MIB.addMBB(TBB); } -unsigned MipsInstrInfo:: -InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl<MachineOperand> &Cond, - DebugLoc DL) const { +unsigned MipsInstrInfo::InsertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -145,9 +143,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 1; } -unsigned MipsInstrInfo:: -RemoveBranch(MachineBasicBlock &MBB) const -{ +unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); MachineBasicBlock::reverse_iterator FirstBr; unsigned removed; @@ -171,20 +167,18 @@ RemoveBranch(MachineBasicBlock &MBB) const /// ReverseBranchCondition - Return the inverse opcode of the /// specified Branch instruction. -bool MipsInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const -{ +bool MipsInstrInfo::ReverseBranchCondition( + SmallVectorImpl<MachineOperand> &Cond) const { assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); return false; } -MipsInstrInfo::BranchType MipsInstrInfo:: -AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, - bool AllowModify, - SmallVectorImpl<MachineInstr*> &BranchInstrs) const { +MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch( + MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, + SmallVectorImpl<MachineInstr *> &BranchInstrs) const { MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); |

