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| author | Craig Topper <craig.topper@intel.com> | 2019-09-27 18:23:55 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-27 18:23:55 +0000 |
| commit | 750bdda6388668b4fea655ced20bd4e59fe6c968 (patch) | |
| tree | c759c891818ccef9932a77bda9a55517e512ed7f | |
| parent | 432a88bf04532f2bf800963f074d82787ad1dec2 (diff) | |
| download | bcm5719-llvm-750bdda6388668b4fea655ced20bd4e59fe6c968.tar.gz bcm5719-llvm-750bdda6388668b4fea655ced20bd4e59fe6c968.zip | |
[X86] Call SimplifyDemandedBits in combineGatherScatter any time the mask element is wider than i1, not just when AVX512 is disabled.
The AVX2 intrinsics can still be used when AVX512 is enabled and
those go through this path. So we should simplify them.
llvm-svn: 373108
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll | 2 |
2 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ff927a4df92..77a7489a2b5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -43425,10 +43425,10 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG, } } - // With AVX2 we only demand the upper bit of the mask. - if (!Subtarget.hasAVX512()) { + // With vector masks we only demand the upper bit of the mask. + SDValue Mask = N->getOperand(2); + if (Mask.getScalarValueSizeInBits() != 1) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - SDValue Mask = N->getOperand(2); APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits())); if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) return SDValue(N, 0); diff --git a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll index 17e48762dad..5721c699852 100644 --- a/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll +++ b/llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll @@ -2205,7 +2205,6 @@ define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, i8* %a1, <2 x i64> %idx ; X86-AVX512VL: # %bb.0: ; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-AVX512VL-NEXT: vpsllq $63, %xmm2, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0x73,0xf2,0x3f] -; X86-AVX512VL-NEXT: vpsraq $63, %xmm2, %xmm2 # encoding: [0x62,0xf1,0xed,0x08,0x72,0xe2,0x3f] ; X86-AVX512VL-NEXT: vpgatherqq %xmm2, (%eax,%xmm1,2), %xmm0 # encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x48] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; @@ -2218,7 +2217,6 @@ define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, i8* %a1, <2 x i64> %idx ; X64-AVX512VL-LABEL: test_mask_demanded_bits: ; X64-AVX512VL: # %bb.0: ; X64-AVX512VL-NEXT: vpsllq $63, %xmm2, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0x73,0xf2,0x3f] -; X64-AVX512VL-NEXT: vpsraq $63, %xmm2, %xmm2 # encoding: [0x62,0xf1,0xed,0x08,0x72,0xe2,0x3f] ; X64-AVX512VL-NEXT: vpgatherqq %xmm2, (%rdi,%xmm1,2), %xmm0 # encoding: [0xc4,0xe2,0xe9,0x91,0x04,0x4f] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3] %mask1 = sext <2 x i1> %mask to <2 x i64> |
