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| author | Craig Topper <craig.topper@gmail.com> | 2016-05-18 06:55:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-05-18 06:55:59 +0000 |
| commit | 74ed087b0b0d95855d7f8118d712996a8e96c3a4 (patch) | |
| tree | 095de887288888f9b3e43f00a5f089e2370e8ae9 | |
| parent | 4b23ed79b303960d1edd86b116afc4b920337a0b (diff) | |
| download | bcm5719-llvm-74ed087b0b0d95855d7f8118d712996a8e96c3a4.tar.gz bcm5719-llvm-74ed087b0b0d95855d7f8118d712996a8e96c3a4.zip | |
[AVX512] Strengthen type checks on the X86ISD::SELECT node. Saves over 800 bytes in the DAG isel table by removing type checks for the condition operand which is always a vector or scalar of i1 matching the the number of elements in the other operands.
llvm-svn: 269885
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 11 |
2 files changed, 16 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0f5c7f36903..54b8c942802 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -268,8 +268,8 @@ multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _, !con((ins _.RC:$src0, _.KRCWM:$mask), Ins), !con((ins _.KRCWM:$mask), Ins), OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS, - (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select, - "$src0 = $dst", itin, IsCommutable>; + (X86selects _.KRCWM:$mask, RHS, _.RC:$src0), + X86selects, "$src0 = $dst", itin, IsCommutable>; // Similar to AVX512_maskable but in this case one of the source operands // ($src1) is already tied to $dst so we just use that for the preserved @@ -311,7 +311,8 @@ multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _, !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns), !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns), OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS, - (X86select _.KRCWM:$mask, RHS, _.RC:$src1), X86select>; + (X86selects _.KRCWM:$mask, RHS, _.RC:$src1), + X86selects>; multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, @@ -2919,11 +2920,11 @@ defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>, defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>, VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>; -def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), +def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))), (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X), VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>; -def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), +def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))), (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X), VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>; diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index 2ec730c5f0d..67328b12d2d 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -274,7 +274,16 @@ def X86testnm : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>; def X86movmsk : SDNode<"X86ISD::MOVMSK", SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; -def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>; +def X86select : SDNode<"X86ISD::SELECT", + SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<2, 3>, + SDTCisSameNumEltsAs<0, 1>]>>; + +def X86selects : SDNode<"X86ISD::SELECT", + SDTypeProfile<1, 3, [SDTCisVT<1, i1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<2, 3>]>>; def X86pmuludq : SDNode<"X86ISD::PMULUDQ", SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>, |
