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authorDavid Green <david.green@arm.com>2019-02-14 11:09:24 +0000
committerDavid Green <david.green@arm.com>2019-02-14 11:09:24 +0000
commit743abf2bd920640dbb4cc7b900fe5d4fa25caafa (patch)
tree709e4753a70ca82ed02f971cceb6f2fcc8ae0ae7
parentd27cf27eb1fe49a244260e53df8e93a1dc10f7c8 (diff)
downloadbcm5719-llvm-743abf2bd920640dbb4cc7b900fe5d4fa25caafa.tar.gz
bcm5719-llvm-743abf2bd920640dbb4cc7b900fe5d4fa25caafa.zip
[ARM] Ensure we update the correct flags in the peephole optimiser
The Arm peephole optimiser code keeps track of both an MI and a SubAdd that can be used to optimise away a CMP. In the rare case that both are found and not ruled-out as valid, we could end up setting the flags on the wrong one. Instead make sure we are using SubAdd if it exists, as it will be closer to the CMP. The testcase here is a little theoretical, with a dead def of cpsr. It should hopefully show the point. Differential Revision: https://reviews.llvm.org/D58176 llvm-svn: 354018
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp7
-rw-r--r--llvm/test/CodeGen/Thumb2/peephole-addsub.mir35
2 files changed, 40 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9c8fed0e223..a23ae20858e 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2825,8 +2825,11 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
if (!MI && !SubAdd)
return false;
- // The single candidate is called MI.
- if (!MI) MI = SubAdd;
+ // If we found a SubAdd, use it as it will be closer to the CMP
+ if (SubAdd) {
+ MI = SubAdd;
+ IsThumb1 = false;
+ }
// We can't use a predicated instruction - it doesn't always write the flags.
if (isPredicated(*MI))
diff --git a/llvm/test/CodeGen/Thumb2/peephole-addsub.mir b/llvm/test/CodeGen/Thumb2/peephole-addsub.mir
new file mode 100644
index 00000000000..f9d7a838c6a
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/peephole-addsub.mir
@@ -0,0 +1,35 @@
+# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
+--- |
+ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv7-none-eabi"
+
+ define i32 @test(i32 %a, i32 %b) {
+ unreachable
+ }
+
+...
+---
+name: test
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '%0' }
+ - { reg: '$r1', virtual-reg: '%1' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ %1:rgpr = COPY $r1
+ %0:rgpr = COPY $r0
+ %2:rgpr = t2MOVi 1, 14, $noreg, $noreg
+ %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
+ %4:gprnopc = t2SUBri %3, 0, 14, $noreg, def dead $cpsr
+ t2CMPri killed %3, 0, 14, $noreg, implicit-def $cpsr
+ %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
+ $r0 = COPY %5
+ tBX_RET 14, $noreg, implicit $r0
+
+# CHECK-LABEL: name: test
+# CHECK: %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg
+# CHECK-NEXT: %4:gprnopc = t2SUBri %3, 0, 14, $noreg, def $cpsr
+# CHECK-NEXT: %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr
+...
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