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| author | Pengfei Wang <pengfei.wang@intel.com> | 2019-05-29 02:49:59 +0000 |
|---|---|---|
| committer | Pengfei Wang <pengfei.wang@intel.com> | 2019-05-29 02:49:59 +0000 |
| commit | 72e3f9662b702fb407012d59ef0c23be2a3c7c7c (patch) | |
| tree | bb81d87b0a801d6bdef2210d61f480aa83604278 | |
| parent | 82705e7d52b46ea6067cd75af6c16c695de99b1d (diff) | |
| download | bcm5719-llvm-72e3f9662b702fb407012d59ef0c23be2a3c7c7c.tar.gz bcm5719-llvm-72e3f9662b702fb407012d59ef0c23be2a3c7c7c.zip | |
Revert "[X86] Use 'llvm_unreachable' instead of nullptr in unreachable code to"
This reverts commit c1b3716614bc0a107e6f41a7d3d503baefad8a5b.
llvm-svn: 361918
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstructionSelector.cpp | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index c2fa813c7d7..55f10a2d065 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -91,9 +91,7 @@ RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, return RB; if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>()) return &getRegBankFromRegClass(*RC); - - llvm_unreachable("RegClassOrBank is either a const RegisterBank* or " - "a const TargetRegisterClass*"); + return nullptr; } const TargetRegisterClass & diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp index e52ee03f34a..61de562f8a5 100644 --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp @@ -1610,8 +1610,8 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && "Arguments and return value types must match"); - const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI); - if (RegRB.getID() != X86::GPRRegBankID) + const RegisterBank *RegRB = RBI.getRegBank(DstReg, MRI, TRI); + if (!RegRB || RegRB->getID() != X86::GPRRegBankID) return false; const static unsigned NumTypes = 4; // i8, i16, i32, i64 @@ -1709,7 +1709,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I, const DivRemEntry &TypeEntry = *OpEntryIt; const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; - const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB); + const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) || !RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) { |
