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| author | Bob Wilson <bob.wilson@apple.com> | 2010-08-05 18:59:36 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-08-05 18:59:36 +0000 |
| commit | 72de3071160f58b7400a1d7a5c571bb780331b80 (patch) | |
| tree | 007aa50b8db3e0c4b04f53b3d5db3555d615a75d | |
| parent | 32f5d6b9be7bffbbca6b8841d2913589c9b00b27 (diff) | |
| download | bcm5719-llvm-72de3071160f58b7400a1d7a5c571bb780331b80.tar.gz bcm5719-llvm-72de3071160f58b7400a1d7a5c571bb780331b80.zip | |
Add an ARM RSCrr instruction for disassembly only.
Partial fix for PR7792.
llvm-svn: 110361
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/arm-tests.txt | 4 |
2 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 2ca24153138..3c710db38c7 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1673,6 +1673,14 @@ def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), Requires<[IsARM]> { let Inst{25} = 1; } +// The reg/reg form is only defined for the disassembler; for codegen it is +// equivalent to SUBrr. +def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b), + DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b", + [/* For disassembly only; pattern left blank */]> { + let Inst{25} = 0; + let Inst{11-4} = 0b00000000; +} def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b", [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>, diff --git a/llvm/test/MC/Disassembler/arm-tests.txt b/llvm/test/MC/Disassembler/arm-tests.txt index 242d5ec1102..52161a6ec16 100644 --- a/llvm/test/MC/Disassembler/arm-tests.txt +++ b/llvm/test/MC/Disassembler/arm-tests.txt @@ -65,6 +65,10 @@ # CHECK: rsbeq r0, r2, r0 0x00 0x00 0x62 0x00 +# CHECK-NOT: rsceqs r0, r0, r1, lsl #0 +# CHECK: rsceqs r0, r0, r1 +0x01 0x00 0xf0 0x00 + # CHECK: sbcs r0, pc, #1 0x01 0x00 0xdf 0xe2 |
