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| author | Luis Marques <luismarques@lowrisc.org> | 2019-03-26 15:41:45 +0000 |
|---|---|---|
| committer | Luis Marques <luismarques@lowrisc.org> | 2019-03-26 15:41:45 +0000 |
| commit | 72734fc7b5fbbf4be0dd38cffc468e5664981e07 (patch) | |
| tree | ffe201e2435be107ebc33882ed7cbd24f84dc508 | |
| parent | 9d568e29b79be8875b0c519598efd24baef61c31 (diff) | |
| download | bcm5719-llvm-72734fc7b5fbbf4be0dd38cffc468e5664981e07.tar.gz bcm5719-llvm-72734fc7b5fbbf4be0dd38cffc468e5664981e07.zip | |
[RISCV] Update setcc-logic.ll codegen test
This should have been updated as part of D59753.
llvm-svn: 357002
| -rw-r--r-- | llvm/test/CodeGen/RISCV/setcc-logic.ll | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll index 2303e556346..72f797db15a 100644 --- a/llvm/test/CodeGen/RISCV/setcc-logic.ll +++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll @@ -102,26 +102,22 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind { define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { ; RV32I-LABEL: and_icmps_const_not1bit_diff: ; RV32I: # %bb.0: -; RV32I-NEXT: addi a1, zero, 44 -; RV32I-NEXT: xor a1, a0, a1 -; RV32I-NEXT: addi a2, zero, 92 -; RV32I-NEXT: xor a0, a0, a2 -; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: xori a1, a0, 92 ; RV32I-NEXT: snez a1, a1 -; RV32I-NEXT: and a0, a1, a0 +; RV32I-NEXT: xori a0, a0, 44 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: and_icmps_const_not1bit_diff: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 -; RV64I-NEXT: addi a1, zero, 44 -; RV64I-NEXT: xor a1, a0, a1 -; RV64I-NEXT: addi a2, zero, 92 -; RV64I-NEXT: xor a0, a0, a2 -; RV64I-NEXT: snez a0, a0 +; RV64I-NEXT: xori a1, a0, 92 ; RV64I-NEXT: snez a1, a1 -; RV64I-NEXT: and a0, a1, a0 +; RV64I-NEXT: xori a0, a0, 44 +; RV64I-NEXT: snez a0, a0 +; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret %a = icmp ne i32 %x, 44 %b = icmp ne i32 %x, 92 |
