diff options
| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-03 16:01:44 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-03 16:01:44 +0000 |
| commit | 7258735fa0b60dd7800f5b9859aceeee16bb4990 (patch) | |
| tree | dd939e484bbcf0c57181107f7366c0bb8bbfa41e | |
| parent | 01b4aa94371345be8e19129ccd9c6814f9c0e6aa (diff) | |
| download | bcm5719-llvm-7258735fa0b60dd7800f5b9859aceeee16bb4990.tar.gz bcm5719-llvm-7258735fa0b60dd7800f5b9859aceeee16bb4990.zip | |
ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.
Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.
llvm-svn: 205541
222 files changed, 565 insertions, 335 deletions
diff --git a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll index 758b59a4638..dd9a6fd12d7 100644 --- a/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll +++ b/llvm/test/CodeGen/ARM/2009-09-13-InvalidSuperReg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a9 +; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind { %1 = ptrtoint i8* %pBuffer to i32 diff --git a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll index eb9c2d0f7f8..224bd019481 100644 --- a/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/llvm/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; pr4926 define void @test_vget_lanep16() nounwind { diff --git a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll index b0b4cb37d1a..5e75d460aa7 100644 --- a/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll +++ b/llvm/test/CodeGen/ARM/2010-03-04-stm-undef-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) { %1 = sub i32 undef, 48 ; <i32> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll index 89d6a68fcae..ceef0830fd2 100644 --- a/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/llvm/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=arm -mattr=+neon < %s -; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null +; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values. define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll index 5d0c3cf74aa..cb3e04259ae 100644 --- a/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/llvm/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=arm1136jf-s +; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null ; Radar 7854640 define void @test() nounwind { diff --git a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll index e0f50c97ba5..cfaffd8234b 100644 --- a/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll +++ b/llvm/test/CodeGen/ARM/2010-05-20-NEONSpillCrash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 -optimize-regalloc -regalloc=basic +; RUN: llc -mtriple=arm-eabi -mattr=+neon -O0 -optimize-regalloc -regalloc=basic %s -o /dev/null ; This test would crash the rewriter when trying to handle a spill after one of ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register. diff --git a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll index a400b7b288c..5bc08b037a1 100644 --- a/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/llvm/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; Radar 7872877 define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { diff --git a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index 6f487962310..f7ceb6e7e48 100644 --- a/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/llvm/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+neon -; Radar 8084742 +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null +; rdar://8084742 %struct.__int8x8x2_t = type { [2 x <8 x i8>] } diff --git a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll index 984583e8068..fcabc900afa 100644 --- a/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll +++ b/llvm/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null @.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll index 850c51133f3..c8e08c22ab1 100644 --- a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll +++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; Trigger multiple NEON stores. ; CHECK: vst1.64 diff --git a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll index 8a65f2e82b7..a707a92c9fa 100644 --- a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll +++ b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; PR11319 @i8_res = global <2 x i8> <i8 0, i8 0> diff --git a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll index 42eb32d14c7..c1554d848c4 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; PR11319 @src1_v2i16 = global <2 x i16> <i16 0, i16 1> diff --git a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll index 719571b3d1f..c50461a42d8 100644 --- a/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll +++ b/llvm/test/CodeGen/ARM/2011-11-09-IllegalVectorFPIntConvert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <2 x i32> @test1(<2 x double>* %A) { ; CHECK: test1 diff --git a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 1d2be314851..86b58c8186b 100644 --- a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mcpu=cortex-a9 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=cortex-a9 %s -o - | FileCheck %s @A = global <4 x float> <float 0., float 1., float 2., float 3.> diff --git a/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll b/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll index 089dc9153af..9b71be23b7e 100644 --- a/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll +++ b/llvm/test/CodeGen/ARM/2012-04-10-DAGCombine.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a9 -enable-unsafe-fp-math +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -enable-unsafe-fp-math %s -o /dev/null ;target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" ;target triple = "armv7-none-linux-gnueabi" diff --git a/llvm/test/CodeGen/ARM/2012-05-04-vmov.ll b/llvm/test/CodeGen/ARM/2012-05-04-vmov.ll index 14dbf7ff4ac..c604eed3dd0 100644 --- a/llvm/test/CodeGen/ARM/2012-05-04-vmov.ll +++ b/llvm/test/CodeGen/ARM/2012-05-04-vmov.ll @@ -1,5 +1,9 @@ -; RUN: llc -O1 -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=A9-CHECK %s -; RUN: llc -O1 -march=arm -mcpu=swift < %s | FileCheck -check-prefix=SWIFT-CHECK %s +; RUN: llc -O1 -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ +; RUN: | FileCheck -check-prefix=A9-CHECK %s + +; RUN: llc -O1 -mtriple=arm-eabi -mcpu=swift %s -o - \ +; RUN: | FileCheck -check-prefix=SWIFT-CHECK %s + ; Check that swift doesn't use vmov.32. <rdar://problem/10453003>. define <2 x i32> @testuvec(<2 x i32> %A, <2 x i32> %B) nounwind { diff --git a/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll b/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll index dd678436c04..7f30ae10e43 100644 --- a/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll +++ b/llvm/test/CodeGen/ARM/2012-05-10-PreferVMOVtoVDUP32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm -mcpu=swift < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s ; <rdar://problem/10451892> define void @f(i32 %x, i32* %p) nounwind ssp { diff --git a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll index 647ebd6bdfd..e8d4fb22a59 100644 --- a/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll +++ b/llvm/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; PR12281 ; Test generataion of code for vmull instruction when multiplying 128-bit diff --git a/llvm/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll b/llvm/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll index 3bdbb3cf580..8d777634f6c 100644 --- a/llvm/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll +++ b/llvm/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=arm7tdmi | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=arm7tdmi %s -o - | FileCheck %s ; movw is only legal for V6T2 and later. ; rdar://12300648 diff --git a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll index 38624e0641f..5235e9cb203 100644 --- a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll +++ b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s ; Check for error message: ; CHECK: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type diff --git a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll index 7ba693d6df4..d389b5c5c1c 100644 --- a/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll +++ b/llvm/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s ; Check for error message: ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type diff --git a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index 60f361e7cb0..6c0fbd00bd1 100644 --- a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+neon -print-before=post-RA-sched > %t 2>&1 && FileCheck < %t %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \ +; RUN: | FileCheck %s define void @vst(i8* %m, [4 x i64] %v) { entry: diff --git a/llvm/test/CodeGen/ARM/DbgValueOtherTargets.test b/llvm/test/CodeGen/ARM/DbgValueOtherTargets.test index bf90891de0a..9ce2459cd81 100644 --- a/llvm/test/CodeGen/ARM/DbgValueOtherTargets.test +++ b/llvm/test/CodeGen/ARM/DbgValueOtherTargets.test @@ -1 +1 @@ -RUN: llc -O0 -march=arm -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -mtriple=arm-eabi -asm-verbose %S/../Inputs/DbgValueOtherTargets.ll -o - | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/llvm/test/CodeGen/ARM/a15-mla.ll b/llvm/test/CodeGen/ARM/a15-mla.ll index b233cc27c4b..9867e27ba7f 100644 --- a/llvm/test/CodeGen/ARM/a15-mla.ll +++ b/llvm/test/CodeGen/ARM/a15-mla.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \ +; RUN: | FileCheck %s ; This test checks that the VMLxForwarting feature is disabled for A15. ; CHECK: fun_a: diff --git a/llvm/test/CodeGen/ARM/a15.ll b/llvm/test/CodeGen/ARM/a15.ll index 5094332380c..9f0b2809a95 100644 --- a/llvm/test/CodeGen/ARM/a15.ll +++ b/llvm/test/CodeGen/ARM/a15.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a15 | FileCheck %s +; RUN: llc -mtriple=arm -mcpu=cortex-a15 %s -o - | FileCheck %s ; CHECK: a define i32 @a(i32 %x) { diff --git a/llvm/test/CodeGen/ARM/addrmode.ll b/llvm/test/CodeGen/ARM/addrmode.ll index 748d2580444..8fd1da791f1 100644 --- a/llvm/test/CodeGen/ARM/addrmode.ll +++ b/llvm/test/CodeGen/ARM/addrmode.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=arm -stats 2>&1 | grep asm-printer | grep 4 +; RUN: llc -mtriple=arm-eabi -stats %s -o - 2>&1 | FileCheck %s define i32 @t1(i32 %a) { %b = mul i32 %a, 9 @@ -14,3 +14,6 @@ define i32 @t2(i32 %a) { %d = load i32* %c ret i32 %d } + +; CHECK: 4 asm-printer + diff --git a/llvm/test/CodeGen/ARM/addrspacecast.ll b/llvm/test/CodeGen/ARM/addrspacecast.ll index 2e98ba53c67..7b6237d719d 100644 --- a/llvm/test/CodeGen/ARM/addrspacecast.ll +++ b/llvm/test/CodeGen/ARM/addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null ; Check that codegen for an addrspace cast succeeds without error. define <4 x i32 addrspace(1)*> @f (<4 x i32*> %x) { diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll index 3373455224e..bf827d6b66e 100644 --- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s -; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s -; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 \ +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck -check-prefix=ARM %s +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck -check-prefix=THUMB %s +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ ; RUN: | FileCheck -check-prefix=T2 %s -; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=V8 %s +; RUN: llc -mtriple=thumbv8-eabi %s -o - | FileCheck -check-prefix=V8 %s ; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified. diff --git a/llvm/test/CodeGen/ARM/arm-asm.ll b/llvm/test/CodeGen/ARM/arm-asm.ll index 2e35e3953f7..e869abeb2dd 100644 --- a/llvm/test/CodeGen/ARM/arm-asm.ll +++ b/llvm/test/CodeGen/ARM/arm-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define void @frame_dummy() { entry: diff --git a/llvm/test/CodeGen/ARM/arm-modifier.ll b/llvm/test/CodeGen/ARM/arm-modifier.ll index f943aea9e1d..580f7e7a90c 100644 --- a/llvm/test/CodeGen/ARM/arm-modifier.ll +++ b/llvm/test/CodeGen/ARM/arm-modifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 -no-integrated-as %s -o - | FileCheck %s define i32 @foo(float %scale, float %scale2) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/arm-negative-stride.ll b/llvm/test/CodeGen/ARM/arm-negative-stride.ll index fb0f8ff8790..7decb974e26 100644 --- a/llvm/test/CodeGen/ARM/arm-negative-stride.ll +++ b/llvm/test/CodeGen/ARM/arm-negative-stride.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; This loop is rewritten with an indvar which counts down, which ; frees up a register from holding the trip count. diff --git a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll index 1a7092a430d..68bf71486a2 100644 --- a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll +++ b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s ; CHECK-LABEL: max: define i32 @max(i8 %ctx, i32* %ptr, i32 %val) diff --git a/llvm/test/CodeGen/ARM/bfc.ll b/llvm/test/CodeGen/ARM/bfc.ll index 3a17d2b8cf9..1162aacee66 100644 --- a/llvm/test/CodeGen/ARM/bfc.ll +++ b/llvm/test/CodeGen/ARM/bfc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s ; 4278190095 = 0xff00000f define i32 @f1(i32 %a) { diff --git a/llvm/test/CodeGen/ARM/bfi.ll b/llvm/test/CodeGen/ARM/bfi.ll index 72a46780997..bce09da7618 100644 --- a/llvm/test/CodeGen/ARM/bfi.ll +++ b/llvm/test/CodeGen/ARM/bfi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck %s +; RUN: llc -mtriple=arm -mattr=+v6t2 %s -o - | FileCheck %s %struct.F = type { [3 x i8], i8 } diff --git a/llvm/test/CodeGen/ARM/bfx.ll b/llvm/test/CodeGen/ARM/bfx.ll index 394da9e157f..46f49e9fab2 100644 --- a/llvm/test/CodeGen/ARM/bfx.ll +++ b/llvm/test/CodeGen/ARM/bfx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s define i32 @sbfx1(i32 %a) { ; CHECK: sbfx1 diff --git a/llvm/test/CodeGen/ARM/bic.ll b/llvm/test/CodeGen/ARM/bic.ll index 1dfd6278287..691f8be4ab6 100644 --- a/llvm/test/CodeGen/ARM/bic.ll +++ b/llvm/test/CodeGen/ARM/bic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 diff --git a/llvm/test/CodeGen/ARM/bits.ll b/llvm/test/CodeGen/ARM/bits.ll index ce1b2ad5fad..14aa27e90b6 100644 --- a/llvm/test/CodeGen/ARM/bits.ll +++ b/llvm/test/CodeGen/ARM/bits.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(i32 %a, i32 %b) { entry: diff --git a/llvm/test/CodeGen/ARM/call.ll b/llvm/test/CodeGen/ARM/call.ll index 107e79a9e01..f6301cf0203 100644 --- a/llvm/test/CodeGen/ARM/call.ll +++ b/llvm/test/CodeGen/ARM/call.ll @@ -1,7 +1,11 @@ -; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4 -; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -mtriple=armv6-linux-gnueabi\ -; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - \ +; RUN: | FileCheck %s -check-prefix=CHECKV4 + +; RUN: llc -mtriple=arm-eabi -mattr=+v5t %s -o - \ +; RUN: | FileCheck %s -check-prefix=CHECKV5 + +; RUN: llc -mtriple=armv6-linux-gnueabi -relocation-model=pic %s -o - \ +; RUN: | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/carry.ll b/llvm/test/CodeGen/ARM/carry.ll index f67987f8eb6..e344b08a8ae 100644 --- a/llvm/test/CodeGen/ARM/carry.ll +++ b/llvm/test/CodeGen/ARM/carry.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i64 @f1(i64 %a, i64 %b) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/clz.ll b/llvm/test/CodeGen/ARM/clz.ll index 5b6a584bbee..68e8c7cef1b 100644 --- a/llvm/test/CodeGen/ARM/clz.ll +++ b/llvm/test/CodeGen/ARM/clz.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v5t %s -o - | FileCheck %s declare i32 @llvm.ctlz.i32(i32, i1) diff --git a/llvm/test/CodeGen/ARM/compare-call.ll b/llvm/test/CodeGen/ARM/compare-call.ll index fac2bc5e432..323eb1f2dd3 100644 --- a/llvm/test/CodeGen/ARM/compare-call.ll +++ b/llvm/test/CodeGen/ARM/compare-call.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \ -; RUN: grep vcmpe.f32 +; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s define void @test3(float* %glob, i32 %X) { entry: @@ -18,3 +17,6 @@ UnifiedReturnBlock: ; preds = %entry } declare i32 @bar(...) + +; CHECK: vcmpe.f32 + diff --git a/llvm/test/CodeGen/ARM/ctz.ll b/llvm/test/CodeGen/ARM/ctz.ll index 2c7efc7c5da..2d88b0351cf 100644 --- a/llvm/test/CodeGen/ARM/ctz.ll +++ b/llvm/test/CodeGen/ARM/ctz.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s declare i32 @llvm.cttz.i32(i32, i1) diff --git a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll index de2820e98a1..4ac5b8a31e5 100644 --- a/llvm/test/CodeGen/ARM/dyn-stackalloc.ll +++ b/llvm/test/CodeGen/ARM/dyn-stackalloc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null %struct.comment = type { i8**, i32*, i32, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } diff --git a/llvm/test/CodeGen/ARM/extload-knownzero.ll b/llvm/test/CodeGen/ARM/extload-knownzero.ll index 8ccf58c3917..f55b95104b8 100644 --- a/llvm/test/CodeGen/ARM/extload-knownzero.ll +++ b/llvm/test/CodeGen/ARM/extload-knownzero.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; rdar://12771555 define void @foo(i16* %ptr, i32 %a) nounwind { diff --git a/llvm/test/CodeGen/ARM/extloadi1.ll b/llvm/test/CodeGen/ARM/extloadi1.ll index dc45ce705f4..2504c6c61e3 100644 --- a/llvm/test/CodeGen/ARM/extloadi1.ll +++ b/llvm/test/CodeGen/ARM/extloadi1.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null + @handler_installed.6144.b = external global i1 ; <i1*> [#uses=1] define void @__mf_sigusr1_respond() { diff --git a/llvm/test/CodeGen/ARM/fadds.ll b/llvm/test/CodeGen/ARM/fadds.ll index 21219ce18e2..b5d3bdae1f9 100644 --- a/llvm/test/CodeGen/ARM/fadds.ll +++ b/llvm/test/CodeGen/ARM/fadds.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP0 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fdivs.ll b/llvm/test/CodeGen/ARM/fdivs.ll index a4fecfe1458..7cab7668900 100644 --- a/llvm/test/CodeGen/ARM/fdivs.ll +++ b/llvm/test/CodeGen/ARM/fdivs.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2 +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NFP0 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fixunsdfdi.ll b/llvm/test/CodeGen/ARM/fixunsdfdi.ll index 6db2385a63e..f3406cc55fb 100644 --- a/llvm/test/CodeGen/ARM/fixunsdfdi.ll +++ b/llvm/test/CodeGen/ARM/fixunsdfdi.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 -; RUN: llc < %s -march=arm -mattr=vfp2 | not grep vstr.64 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null +; RUN: llc -mtriple=arm-eabi -mattr=vfp2 %s -o - | FileCheck %s define hidden i64 @__fixunsdfdi(double %x) nounwind readnone { entry: @@ -27,3 +27,6 @@ bb7: ; preds = %bb3 bb10: ; preds = %entry ret i64 0 } + +; CHECK-NOT: vstr.64 + diff --git a/llvm/test/CodeGen/ARM/fmacs.ll b/llvm/test/CodeGen/ARM/fmacs.ll index f2486c65d3a..6f8c0fe13c9 100644 --- a/llvm/test/CodeGen/ARM/fmacs.ll +++ b/llvm/test/CodeGen/ARM/fmacs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 -; RUN: llc < %s -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s -check-prefix=HARD +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2 +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9 +; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard %s -o - | FileCheck %s -check-prefix=HARD define float @t1(float %acc, float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll b/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll index eb72faf8d81..a3669b42dc6 100644 --- a/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll +++ b/llvm/test/CodeGen/ARM/fmdrr-fmrrd.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmdrr -; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmrrd +; RUN: llc -mtriple=arm-eabi -mattr=vfp2 %s -o - | FileCheck %s ; naive codegen for this is: ; _i: @@ -11,3 +10,8 @@ define i64 @test(double %X) { %Y = bitcast double %X to i64 ret i64 %Y } + +; CHECK-LABEL: test: +; CHECK-NOT: fmdrr +; CHECK-NOT: fmrrd + diff --git a/llvm/test/CodeGen/ARM/fmscs.ll b/llvm/test/CodeGen/ARM/fmscs.ll index f16ec172cb7..5aff74c4cc2 100644 --- a/llvm/test/CodeGen/ARM/fmscs.ll +++ b/llvm/test/CodeGen/ARM/fmscs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2 +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8 define float @t1(float %acc, float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fmuls.ll b/llvm/test/CodeGen/ARM/fmuls.ll index d11f6bd1bd9..b24d867a7e8 100644 --- a/llvm/test/CodeGen/ARM/fmuls.ll +++ b/llvm/test/CodeGen/ARM/fmuls.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP0 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fnegs.ll b/llvm/test/CodeGen/ARM/fnegs.ll index dc4c2e33e49..36af8352433 100644 --- a/llvm/test/CodeGen/ARM/fnegs.ll +++ b/llvm/test/CodeGen/ARM/fnegs.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP0 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA8U + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ +; RUN: | FileCheck %s -check-prefix=CORTEXA9 define float @test1(float* %a) { entry: diff --git a/llvm/test/CodeGen/ARM/fnmacs.ll b/llvm/test/CodeGen/ARM/fnmacs.ll index 825feaa0453..ab35a9769b0 100644 --- a/llvm/test/CodeGen/ARM/fnmacs.ll +++ b/llvm/test/CodeGen/ARM/fnmacs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2 +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8 define float @t1(float %acc, float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/fnmscs.ll b/llvm/test/CodeGen/ARM/fnmscs.ll index 78ccb6095e0..5fa6b219388 100644 --- a/llvm/test/CodeGen/ARM/fnmscs.ll +++ b/llvm/test/CodeGen/ARM/fnmscs.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=A8U -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8U +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=NEON + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=A8 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic %s -o - \ +; RUN: | FileCheck %s -check-prefix=A8 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=A8U + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=A8U define float @t1(float %acc, float %a, float %b) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/fnmul.ll b/llvm/test/CodeGen/ARM/fnmul.ll index 6d7bc05ffa9..e14e5baeb8a 100644 --- a/llvm/test/CodeGen/ARM/fnmul.ll +++ b/llvm/test/CodeGen/ARM/fnmul.ll @@ -1,5 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64 -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64 +; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s + +; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix CHECK-ROUNDING + define double @t1(double %a, double %b) { @@ -9,3 +12,6 @@ entry: ret double %tmp4 } +; CHECK: vnmul.f64 +; CHECK-ROUNDING: vmul.f64 + diff --git a/llvm/test/CodeGen/ARM/fnmuls.ll b/llvm/test/CodeGen/ARM/fnmuls.ll index 3223885feda..de3b053bfc5 100644 --- a/llvm/test/CodeGen/ARM/fnmuls.ll +++ b/llvm/test/CodeGen/ARM/fnmuls.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s define arm_aapcs_vfpcc float @test1(float %a, float %b) nounwind { ; CHECK: vnmul.f32 s0, s0, s1 diff --git a/llvm/test/CodeGen/ARM/fold-const.ll b/llvm/test/CodeGen/ARM/fold-const.ll index 1ba561dd70b..dc5419f24e2 100644 --- a/llvm/test/CodeGen/ARM/fold-const.ll +++ b/llvm/test/CodeGen/ARM/fold-const.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s define i32 @f(i32 %a) nounwind readnone optsize ssp { entry: diff --git a/llvm/test/CodeGen/ARM/formal.ll b/llvm/test/CodeGen/ARM/formal.ll index 4ac10badea9..05a6be1075a 100644 --- a/llvm/test/CodeGen/ARM/formal.ll +++ b/llvm/test/CodeGen/ARM/formal.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null declare void @bar(i64 %x, i64 %y) diff --git a/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll b/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll index ae02b792e4d..4996cc8ecbf 100644 --- a/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll +++ b/llvm/test/CodeGen/ARM/fp-arg-shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -float-abi=soft %s -o - | FileCheck %s ; CHECK: function1 ; CHECK-NOT: vmov diff --git a/llvm/test/CodeGen/ARM/fp-fast.ll b/llvm/test/CodeGen/ARM/fp-fast.ll index ec571873817..7d95a5efe90 100644 --- a/llvm/test/CodeGen/ARM/fp-fast.ll +++ b/llvm/test/CodeGen/ARM/fp-fast.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=arm -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s ; CHECK: test1 define float @test1(float %x) { diff --git a/llvm/test/CodeGen/ARM/fp.ll b/llvm/test/CodeGen/ARM/fp.ll index 888cfa470a3..7e1f000e88d 100644 --- a/llvm/test/CodeGen/ARM/fp.ll +++ b/llvm/test/CodeGen/ARM/fp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s define float @f(i32 %a) { ;CHECK-LABEL: f: diff --git a/llvm/test/CodeGen/ARM/fp_convert.ll b/llvm/test/CodeGen/ARM/fp_convert.ll index f0d910052a4..6f4707573fb 100644 --- a/llvm/test/CodeGen/ARM/fp_convert.ll +++ b/llvm/test/CodeGen/ARM/fp_convert.ll @@ -1,9 +1,20 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=NEON + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=NEON + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 define i32 @test1(float %a, float %b) { ; VFP2-LABEL: test1: diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll index 3a0af16bf6d..eab5988e3eb 100644 --- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll +++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s + ; rdar://7461510 ; rdar://10964603 diff --git a/llvm/test/CodeGen/ARM/fpcmp.ll b/llvm/test/CodeGen/ARM/fpcmp.ll index 916a1ae4952..e3ffd45a396 100644 --- a/llvm/test/CodeGen/ARM/fpcmp.ll +++ b/llvm/test/CodeGen/ARM/fpcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s define i32 @f1(float %a) { ;CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/fpconsts.ll b/llvm/test/CodeGen/ARM/fpconsts.ll index 0679a47ded7..5a45a9bd2ba 100644 --- a/llvm/test/CodeGen/ARM/fpconsts.ll +++ b/llvm/test/CodeGen/ARM/fpconsts.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+vfp3 %s -o - | FileCheck %s define float @t1(float %x) nounwind readnone optsize { entry: diff --git a/llvm/test/CodeGen/ARM/fpconv.ll b/llvm/test/CodeGen/ARM/fpconv.ll index 326e0628b4e..eadf9afd476 100644 --- a/llvm/test/CodeGen/ARM/fpconv.ll +++ b/llvm/test/CodeGen/ARM/fpconv.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP +; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s define float @f1(double %x) { ;CHECK-VFP-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/fpmem.ll b/llvm/test/CodeGen/ARM/fpmem.ll index 966ffee053f..3a454ed9631 100644 --- a/llvm/test/CodeGen/ARM/fpmem.ll +++ b/llvm/test/CodeGen/ARM/fpmem.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s +; RUN: llc -mtriple=arm -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s define float @f1(float %a) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/fpow.ll b/llvm/test/CodeGen/ARM/fpow.ll index 6d487927ee6..3e37724d1c5 100644 --- a/llvm/test/CodeGen/ARM/fpow.ll +++ b/llvm/test/CodeGen/ARM/fpow.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define double @t(double %x, double %y) nounwind optsize { entry: diff --git a/llvm/test/CodeGen/ARM/fptoint.ll b/llvm/test/CodeGen/ARM/fptoint.ll index 740868725e9..c7217560f48 100644 --- a/llvm/test/CodeGen/ARM/fptoint.ll +++ b/llvm/test/CodeGen/ARM/fptoint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s @i = weak global i32 0 ; <i32*> [#uses=2] @u = weak global i32 0 ; <i32*> [#uses=2] diff --git a/llvm/test/CodeGen/ARM/fsubs.ll b/llvm/test/CodeGen/ARM/fsubs.ll index 617b01881a2..baff34ab31f 100644 --- a/llvm/test/CodeGen/ARM/fsubs.ll +++ b/llvm/test/CodeGen/ARM/fsubs.ll @@ -1,8 +1,17 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1 -; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NFP1U -; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1U -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s -check-prefix=VFP2 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP1 + +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP1U + +; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP1U + +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \ +; RUN: | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: diff --git a/llvm/test/CodeGen/ARM/hello.ll b/llvm/test/CodeGen/ARM/hello.ll index 893b4266ac3..d2685854dba 100644 --- a/llvm/test/CodeGen/ARM/hello.ll +++ b/llvm/test/CodeGen/ARM/hello.ll @@ -1,8 +1,11 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 -; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ -; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=armv6-apple-ios | grep mov | count 2 +; RUN: llc -mtriple=arm-eabi %s -o /dev/null +; RUN: llc -mtriple=armv6-linux-gnueabi %s -o - | FileCheck %s + +; RUN: llc -mtriple=armv6-linux-gnu --disable-fp-elim %s -o - \ +; RUN: | FileCheck %s -check-prefix CHECK-FP-ELIM + +; RUN: llc -mtriple=armv6-apple-ios %s -o - \ +; RUN: | FileCheck %s -check-prefix CHECK-FP-ELIM @str = internal constant [12 x i8] c"Hello World\00" @@ -12,3 +15,11 @@ define i32 @main() { } declare i32 @puts(i8*) + +; CHECK: mov +; CHECK-NOT: mov + +; CHECK-FP-ELIM: mov +; CHECK-FP-ELIM: mov +; CHECK-FP-ELIM-NOT: mov + diff --git a/llvm/test/CodeGen/ARM/iabs.ll b/llvm/test/CodeGen/ARM/iabs.ll index 600a8c29ea9..c52caf605dd 100644 --- a/llvm/test/CodeGen/ARM/iabs.ll +++ b/llvm/test/CodeGen/ARM/iabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: ;; movs r0, r0 diff --git a/llvm/test/CodeGen/ARM/ifconv-kills.ll b/llvm/test/CodeGen/ARM/ifconv-kills.ll index bf54ba2f730..de80c927cea 100644 --- a/llvm/test/CodeGen/ARM/ifconv-kills.ll +++ b/llvm/test/CodeGen/ARM/ifconv-kills.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march arm -mcpu swift -verify-machineinstrs +; RUN: llc -mtriple arm-eabi -mcpu swift -verify-machineinstrs %s -o /dev/null declare i32 @f(i32 %p0, i32 %p1) diff --git a/llvm/test/CodeGen/ARM/ifcvt1.ll b/llvm/test/CodeGen/ARM/ifcvt1.ll index 5a55653239d..cae2399d873 100644 --- a/llvm/test/CodeGen/ARM/ifcvt1.ll +++ b/llvm/test/CodeGen/ARM/ifcvt1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 -; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8 +; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT define i32 @t1(i32 %a, i32 %b) { ; A8-LABEL: t1: diff --git a/llvm/test/CodeGen/ARM/ifcvt2.ll b/llvm/test/CodeGen/ARM/ifcvt2.ll index e34edecf57e..e445416f6e5 100644 --- a/llvm/test/CodeGen/ARM/ifcvt2.ll +++ b/llvm/test/CodeGen/ARM/ifcvt2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: t1: diff --git a/llvm/test/CodeGen/ARM/ifcvt3.ll b/llvm/test/CodeGen/ARM/ifcvt3.ll index fa7d61887d9..5da63dc5f02 100644 --- a/llvm/test/CodeGen/ARM/ifcvt3.ll +++ b/llvm/test/CodeGen/ARM/ifcvt3.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1 -; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: t1: @@ -22,3 +22,11 @@ cond_next: %tmp15 = add i32 %b, %a ret i32 %tmp15 } + +; CHECK-V4-CMP: cmpne +; CHECK-V4-CMP-NOT: cmpne + +; CHECK-V4-BX: bx +; CHECK-V4-BX: bx +; CHECK-V4-BX-NOT: bx + diff --git a/llvm/test/CodeGen/ARM/ifcvt4.ll b/llvm/test/CodeGen/ARM/ifcvt4.ll index 53c789d184f..8c6825aeda9 100644 --- a/llvm/test/CodeGen/ARM/ifcvt4.ll +++ b/llvm/test/CodeGen/ARM/ifcvt4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; Do not if-convert when branches go to the different loops. ; CHECK-LABEL: t: diff --git a/llvm/test/CodeGen/ARM/ifcvt9.ll b/llvm/test/CodeGen/ARM/ifcvt9.ll index 05bdc459c83..119171627d1 100644 --- a/llvm/test/CodeGen/ARM/ifcvt9.ll +++ b/llvm/test/CodeGen/ARM/ifcvt9.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define fastcc void @t() nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll index febe6f56b66..7208fffbcc8 100644 --- a/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll +++ b/llvm/test/CodeGen/ARM/illegal-vector-bitcast.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=arm-linux +; RUN: llc -mtriple=arm-eabi %s -o /dev/null +; RUN: llc -mtriple=arm-linux %s -o /dev/null define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y) { diff --git a/llvm/test/CodeGen/ARM/imm.ll b/llvm/test/CodeGen/ARM/imm.ll index 6f25f9dcb32..e7bc0afff70 100644 --- a/llvm/test/CodeGen/ARM/imm.ll +++ b/llvm/test/CodeGen/ARM/imm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | not grep CPI +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @test1(i32 %A) { %B = add i32 %A, -268435441 ; <i32> [#uses=1] @@ -14,3 +14,6 @@ define i32 @test3(i32 %A) { ret i32 %B } +; CHECK-NOT: CPI + + diff --git a/llvm/test/CodeGen/ARM/indirect-reg-input.ll b/llvm/test/CodeGen/ARM/indirect-reg-input.ll index b936455975c..17f6a9c96f6 100644 --- a/llvm/test/CodeGen/ARM/indirect-reg-input.ll +++ b/llvm/test/CodeGen/ARM/indirect-reg-input.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s ; Check for error message: ; CHECK: error: inline asm not supported yet: don't know how to handle tied indirect register inputs diff --git a/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll b/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll index 908f093ae27..603e52dd2d7 100644 --- a/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll +++ b/llvm/test/CodeGen/ARM/inlineasm-imm-arm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -no-integrated-as +; RUN: llc -mtriple=arm-eabi -no-integrated-as %s -o /dev/null ; Test ARM-mode "I" constraint, for any Data Processing immediate. define i32 @testI(i32 %x) { diff --git a/llvm/test/CodeGen/ARM/inlineasm.ll b/llvm/test/CodeGen/ARM/inlineasm.ll index cca3c696b4a..39962e08cdd 100644 --- a/llvm/test/CodeGen/ARM/inlineasm.ll +++ b/llvm/test/CodeGen/ARM/inlineasm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6 +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null define i32 @test1(i32 %tmp54) { %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/inlineasm2.ll b/llvm/test/CodeGen/ARM/inlineasm2.ll index a99bccf5a65..5918738cbb2 100644 --- a/llvm/test/CodeGen/ARM/inlineasm2.ll +++ b/llvm/test/CodeGen/ARM/inlineasm2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define double @__ieee754_sqrt(double %x) { %tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x ) diff --git a/llvm/test/CodeGen/ARM/inlineasm3.ll b/llvm/test/CodeGen/ARM/inlineasm3.ll index 8275cca950f..eb7ba59b69b 100644 --- a/llvm/test/CodeGen/ARM/inlineasm3.ll +++ b/llvm/test/CodeGen/ARM/inlineasm3.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as %s -o - \ +; RUN: | FileCheck %s ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } diff --git a/llvm/test/CodeGen/ARM/inlineasm4.ll b/llvm/test/CodeGen/ARM/inlineasm4.ll index 4a1bccaf61c..a117cd2618f 100644 --- a/llvm/test/CodeGen/ARM/inlineasm4.ll +++ b/llvm/test/CodeGen/ARM/inlineasm4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define double @f(double %x) { entry: diff --git a/llvm/test/CodeGen/ARM/insn-sched1.ll b/llvm/test/CodeGen/ARM/insn-sched1.ll index d188fae7034..2749a8e7cd2 100644 --- a/llvm/test/CodeGen/ARM/insn-sched1.ll +++ b/llvm/test/CodeGen/ARM/insn-sched1.ll @@ -1,6 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+v6 -; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6 |\ -; RUN: grep mov | count 3 +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null +; RUN: llc -mtriple=arm-apple-ios -mattr=+v6 %s -o - | FileCheck %s define i32 @test(i32 %x) { %tmp = trunc i32 %x to i16 ; <i16> [#uses=1] @@ -9,3 +8,9 @@ define i32 @test(i32 %x) { } declare i32 @f(i32, i16) + +; CHECK: mov +; CHECK: mov +; CHECK: mov +; CHECK-NOT: mov + diff --git a/llvm/test/CodeGen/ARM/integer_insertelement.ll b/llvm/test/CodeGen/ARM/integer_insertelement.ll index 1d72afefb5b..bf403b92806 100644 --- a/llvm/test/CodeGen/ARM/integer_insertelement.ll +++ b/llvm/test/CodeGen/ARM/integer_insertelement.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -o - -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; This test checks that when inserting one (integer) element into a vector, ; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving diff --git a/llvm/test/CodeGen/ARM/ispositive.ll b/llvm/test/CodeGen/ARM/ispositive.ll index 2f1a2cfd778..3086d7983e1 100644 --- a/llvm/test/CodeGen/ARM/ispositive.ll +++ b/llvm/test/CodeGen/ARM/ispositive.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @test1(i32 %X) { ; CHECK: lsr{{.*}}#31 diff --git a/llvm/test/CodeGen/ARM/large-stack.ll b/llvm/test/CodeGen/ARM/large-stack.ll index ddf0f0ec7cc..1a9a1fadeeb 100644 --- a/llvm/test/CodeGen/ARM/large-stack.ll +++ b/llvm/test/CodeGen/ARM/large-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define void @test1() { %tmp = alloca [ 64 x i32 ] , align 4 diff --git a/llvm/test/CodeGen/ARM/ldr.ll b/llvm/test/CodeGen/ARM/ldr.ll index e4c695b87be..57e9977ff87 100644 --- a/llvm/test/CodeGen/ARM/ldr.ll +++ b/llvm/test/CodeGen/ARM/ldr.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(i32* %v) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/ldr_ext.ll b/llvm/test/CodeGen/ARM/ldr_ext.ll index d29eb022bac..31aaba5c3c2 100644 --- a/llvm/test/CodeGen/ARM/ldr_ext.ll +++ b/llvm/test/CodeGen/ARM/ldr_ext.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @test1(i8* %t1) nounwind { ; CHECK: ldrb diff --git a/llvm/test/CodeGen/ARM/ldr_frame.ll b/llvm/test/CodeGen/ARM/ldr_frame.ll index f071b8922d6..ed964ecd3f8 100644 --- a/llvm/test/CodeGen/ARM/ldr_frame.ll +++ b/llvm/test/CodeGen/ARM/ldr_frame.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s define i32 @f1() { %buf = alloca [32 x i32], align 4 @@ -29,3 +29,6 @@ define i32 @f4() { %tmp2 = zext i8 %tmp1 to i32 ret i32 %tmp2 } + +; CHECK-NOT: mov + diff --git a/llvm/test/CodeGen/ARM/ldr_post.ll b/llvm/test/CodeGen/ARM/ldr_post.ll index f5ff7dda5e0..2558b16f3d3 100644 --- a/llvm/test/CodeGen/ARM/ldr_post.ll +++ b/llvm/test/CodeGen/ARM/ldr_post.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s ; CHECK-LABEL: test1: ; CHECK: ldr {{.*, \[.*]}}, -r2 diff --git a/llvm/test/CodeGen/ARM/ldr_pre.ll b/llvm/test/CodeGen/ARM/ldr_pre.ll index 82818272cf2..a97927a20ab 100644 --- a/llvm/test/CodeGen/ARM/ldr_pre.ll +++ b/llvm/test/CodeGen/ARM/ldr_pre.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | FileCheck %s -; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s ; CHECK-LABEL: test1: ; CHECK: ldr {{.*!}} diff --git a/llvm/test/CodeGen/ARM/load.ll b/llvm/test/CodeGen/ARM/load.ll index 253b0e145f8..ca16adc0082 100644 --- a/llvm/test/CodeGen/ARM/load.ll +++ b/llvm/test/CodeGen/ARM/load.ll @@ -1,9 +1,4 @@ -; RUN: llc < %s -march=arm > %t -; RUN: grep ldrsb %t -; RUN: grep ldrb %t -; RUN: grep ldrsh %t -; RUN: grep ldrh %t - +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(i8* %p) { entry: @@ -32,3 +27,9 @@ entry: %tmp4 = zext i16 %tmp to i32 ; <i32> [#uses=1] ret i32 %tmp4 } + +; CHECK: ldrsb +; CHECK: ldrb +; CHECK: ldrsh +; CHECK: ldrh + diff --git a/llvm/test/CodeGen/ARM/long-setcc.ll b/llvm/test/CodeGen/ARM/long-setcc.ll index c76a5e4d4d1..f09167ed9e7 100644 --- a/llvm/test/CodeGen/ARM/long-setcc.ll +++ b/llvm/test/CodeGen/ARM/long-setcc.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep cmp | count 1 - +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i1 @t1(i64 %x) { %B = icmp slt i64 %x, 0 @@ -15,3 +14,7 @@ define i1 @t3(i32 %x) { %tmp = icmp ugt i32 %x, -1 ret i1 %tmp } + +; CHECK: cmp +; CHECK-NOT: cmp + diff --git a/llvm/test/CodeGen/ARM/long.ll b/llvm/test/CodeGen/ARM/long.ll index 7fffc81797c..d0bff4a906e 100644 --- a/llvm/test/CodeGen/ARM/long.ll +++ b/llvm/test/CodeGen/ARM/long.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i64 @f1() { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/longMAC.ll b/llvm/test/CodeGen/ARM/longMAC.ll index a7ecbf808ed..5636a12c203 100644 --- a/llvm/test/CodeGen/ARM/longMAC.ll +++ b/llvm/test/CodeGen/ARM/longMAC.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | FileCheck %s -; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=CHECK-V7 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s +; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7 ; Check generated signed and unsigned multiply accumulate long. define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) { diff --git a/llvm/test/CodeGen/ARM/long_shift.ll b/llvm/test/CodeGen/ARM/long_shift.ll index 3e986d802d8..48b0ba7ecaa 100644 --- a/llvm/test/CodeGen/ARM/long_shift.ll +++ b/llvm/test/CodeGen/ARM/long_shift.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i64 @f0(i64 %A, i64 %B) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll index 0c8d3874890..948024163ba 100644 --- a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll +++ b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep lsl | grep -F "lsl #2]" +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s ; Should use scaled addressing mode. define void @sintzero(i32* %a) nounwind { @@ -17,3 +17,6 @@ cond_next: ; preds = %cond_next, %entry return: ; preds = %cond_next ret void } + +; CHECK: lsl{{.*}}#2] + diff --git a/llvm/test/CodeGen/ARM/mem.ll b/llvm/test/CodeGen/ARM/mem.ll index f46c7a5857a..3c9cd913add 100644 --- a/llvm/test/CodeGen/ARM/mem.ll +++ b/llvm/test/CodeGen/ARM/mem.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep strb -; RUN: llc < %s -march=arm | grep strh +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define void @f1() { entry: @@ -7,8 +6,13 @@ entry: ret void } +; CHECK: strb + define void @f2() { entry: store i16 0, i16* null ret void } + +; CHECK: strh + diff --git a/llvm/test/CodeGen/ARM/mls.ll b/llvm/test/CodeGen/ARM/mls.ll index 8f0d3a89a30..6776e631f1d 100644 --- a/llvm/test/CodeGen/ARM/mls.ll +++ b/llvm/test/CodeGen/ARM/mls.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+v6t2 -arm-use-mulops=false | FileCheck %s -check-prefix=NO_MULOPS +; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 -arm-use-mulops=false %s -o - \ +; RUN: | FileCheck %s -check-prefix=NO_MULOPS define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b diff --git a/llvm/test/CodeGen/ARM/mul_const.ll b/llvm/test/CodeGen/ARM/mul_const.ll index 482d8f2888c..ada3d4e5b9c 100644 --- a/llvm/test/CodeGen/ARM/mul_const.ll +++ b/llvm/test/CodeGen/ARM/mul_const.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @t9(i32 %v) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/ARM/mulhi.ll b/llvm/test/CodeGen/ARM/mulhi.ll index 63705c50277..c66a804808f 100644 --- a/llvm/test/CodeGen/ARM/mulhi.ll +++ b/llvm/test/CodeGen/ARM/mulhi.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4 -; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3 +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s -check-prefix=V6 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=V4 +; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=M3 define i32 @smulhi(i32 %x, i32 %y) nounwind { ; V6-LABEL: smulhi: diff --git a/llvm/test/CodeGen/ARM/mvn.ll b/llvm/test/CodeGen/ARM/mvn.ll index 2c5ccd7442e..489f2477589 100644 --- a/llvm/test/CodeGen/ARM/mvn.ll +++ b/llvm/test/CodeGen/ARM/mvn.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep mvn | count 9 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1() { entry: @@ -72,3 +72,16 @@ entry: %tmp102 = icmp eq i32 -2, %a ; <i1> [#uses=1] ret i1 %tmp102 } + +; CHECK-LABEL: f1 +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK: mvn +; CHECK-NOT: mvn + diff --git a/llvm/test/CodeGen/ARM/neon_arith1.ll b/llvm/test/CodeGen/ARM/neon_arith1.ll index 58927374177..42e7d82c51d 100644 --- a/llvm/test/CodeGen/ARM/neon_arith1.ll +++ b/llvm/test/CodeGen/ARM/neon_arith1.ll @@ -1,7 +1,10 @@ -; RUN: llc < %s -march=arm -mattr=+neon | grep vadd +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { entry: %0 = add <8 x i8> %a, %b ret <8 x i8> %0 } + +; CHECK: vadd + diff --git a/llvm/test/CodeGen/ARM/neon_cmp.ll b/llvm/test/CodeGen/ARM/neon_cmp.ll index 046b5da2289..e1662c43c64 100644 --- a/llvm/test/CodeGen/ARM/neon_cmp.ll +++ b/llvm/test/CodeGen/ARM/neon_cmp.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s + ; bug 15283 ; radar://13191881 ; CHECK: vfcmp diff --git a/llvm/test/CodeGen/ARM/neon_div.ll b/llvm/test/CodeGen/ARM/neon_div.ll index 4a82c36676f..4f1607ed5ba 100644 --- a/llvm/test/CodeGen/ARM/neon_div.ll +++ b/llvm/test/CodeGen/ARM/neon_div.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source -disable-post-ra | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -pre-RA-sched=source -disable-post-ra %s -o - \ +; RUN: | FileCheck %s define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 diff --git a/llvm/test/CodeGen/ARM/neon_fpconv.ll b/llvm/test/CodeGen/ARM/neon_fpconv.ll index 149f4c77700..8e37ce77818 100644 --- a/llvm/test/CodeGen/ARM/neon_fpconv.ll +++ b/llvm/test/CodeGen/ARM/neon_fpconv.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32. define <2 x float> @vtrunc(<2 x double> %a) { diff --git a/llvm/test/CodeGen/ARM/neon_ld1.ll b/llvm/test/CodeGen/ARM/neon_ld1.ll index 7172a4dfe1a..9fd3fc5f341 100644 --- a/llvm/test/CodeGen/ARM/neon_ld1.ll +++ b/llvm/test/CodeGen/ARM/neon_ld1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s ; CHECK: t1 ; CHECK: vldr d diff --git a/llvm/test/CodeGen/ARM/neon_ld2.ll b/llvm/test/CodeGen/ARM/neon_ld2.ll index 8d215a6e3cd..571a16a061d 100644 --- a/llvm/test/CodeGen/ARM/neon_ld2.ll +++ b/llvm/test/CodeGen/ARM/neon_ld2.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -float-abi=soft -mcpu=swift | FileCheck %s --check-prefix=SWIFT +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=swift %s -o - | FileCheck %s --check-prefix=SWIFT ; CHECK: t1 ; CHECK: vld1.64 diff --git a/llvm/test/CodeGen/ARM/neon_minmax.ll b/llvm/test/CodeGen/ARM/neon_minmax.ll index 2e45919e779..84e4b303c16 100644 --- a/llvm/test/CodeGen/ARM/neon_minmax.ll +++ b/llvm/test/CodeGen/ARM/neon_minmax.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s define float @fmin_ole(float %x) nounwind { ;CHECK-LABEL: fmin_ole: diff --git a/llvm/test/CodeGen/ARM/neon_shift.ll b/llvm/test/CodeGen/ARM/neon_shift.ll index 340f220fb36..3c09358cf13 100644 --- a/llvm/test/CodeGen/ARM/neon_shift.ll +++ b/llvm/test/CodeGen/ARM/neon_shift.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; <rdar://problem/9055897> define <4 x i16> @t1(<4 x i32> %a) nounwind { diff --git a/llvm/test/CodeGen/ARM/neon_vabs.ll b/llvm/test/CodeGen/ARM/neon_vabs.ll index 76b60442398..7a02512198b 100644 --- a/llvm/test/CodeGen/ARM/neon_vabs.ll +++ b/llvm/test/CodeGen/ARM/neon_vabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <4 x i32> @test1(<4 x i32> %a) nounwind { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/ARM/optselect-regclass.ll b/llvm/test/CodeGen/ARM/optselect-regclass.ll index 1aa45208964..0acb2f2f0ec 100644 --- a/llvm/test/CodeGen/ARM/optselect-regclass.ll +++ b/llvm/test/CodeGen/ARM/optselect-regclass.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs +; RUN: llc -mtriple=arm-eabi -mcpu=swift -verify-machineinstrs %s -o /dev/null + %union.opcode.0.2.5.8.15.28 = type { i32 } @opcode = external global %union.opcode.0.2.5.8.15.28, align 4 diff --git a/llvm/test/CodeGen/ARM/pack.ll b/llvm/test/CodeGen/ARM/pack.ll index fbc115518f8..89abe28b0f5 100644 --- a/llvm/test/CodeGen/ARM/pack.ll +++ b/llvm/test/CodeGen/ARM/pack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s ; CHECK: test1 ; CHECK: pkhbt r0, r0, r1, lsl #16 diff --git a/llvm/test/CodeGen/ARM/phi.ll b/llvm/test/CodeGen/ARM/phi.ll index dc1a95b0b78..94bced5200c 100644 --- a/llvm/test/CodeGen/ARM/phi.ll +++ b/llvm/test/CodeGen/ARM/phi.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s + ; <rdar://problem/8686347> define i32 @test1(i1 %a, i32* %b) { diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll index bdf793d91b0..7ace640c6b6 100644 --- a/llvm/test/CodeGen/ARM/popcnt.ll +++ b/llvm/test/CodeGen/ARM/popcnt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; Implement ctpop with vcnt define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { diff --git a/llvm/test/CodeGen/ARM/prefetch.ll b/llvm/test/CodeGen/ARM/prefetch.ll index e6cc849380a..7350e0a90d8 100644 --- a/llvm/test/CodeGen/ARM/prefetch.ll +++ b/llvm/test/CodeGen/ARM/prefetch.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP +; RUN: llc -mtriple=thumb-eabi -mattr=-thumb2 %s -o - | FileCheck %s -check-prefix CHECK-T1 +; RUN: llc -mtriple=thumb-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=THUMB2 +; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=ARM +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9-mp %s -o - | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 +; CHECK-T1-NOT: pld + define void @t1(i8* %ptr) nounwind { entry: ; ARM-LABEL: t1: diff --git a/llvm/test/CodeGen/ARM/ret0.ll b/llvm/test/CodeGen/ARM/ret0.ll index 5c312eb98a3..e51067b7ad5 100644 --- a/llvm/test/CodeGen/ARM/ret0.ll +++ b/llvm/test/CodeGen/ARM/ret0.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define i32 @test() { ret i32 0 diff --git a/llvm/test/CodeGen/ARM/ret_arg1.ll b/llvm/test/CodeGen/ARM/ret_arg1.ll index 1ab947b1e20..b7eef205996 100644 --- a/llvm/test/CodeGen/ARM/ret_arg1.ll +++ b/llvm/test/CodeGen/ARM/ret_arg1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define i32 @test(i32 %a1) { ret i32 %a1 diff --git a/llvm/test/CodeGen/ARM/ret_arg2.ll b/llvm/test/CodeGen/ARM/ret_arg2.ll index 84477d042c7..bcb379b7d6a 100644 --- a/llvm/test/CodeGen/ARM/ret_arg2.ll +++ b/llvm/test/CodeGen/ARM/ret_arg2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define i32 @test(i32 %a1, i32 %a2) { ret i32 %a2 diff --git a/llvm/test/CodeGen/ARM/ret_arg3.ll b/llvm/test/CodeGen/ARM/ret_arg3.ll index f7f9057432d..625162f7762 100644 --- a/llvm/test/CodeGen/ARM/ret_arg3.ll +++ b/llvm/test/CodeGen/ARM/ret_arg3.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null + define i32 @test(i32 %a1, i32 %a2, i32 %a3) { ret i32 %a3 } diff --git a/llvm/test/CodeGen/ARM/ret_arg4.ll b/llvm/test/CodeGen/ARM/ret_arg4.ll index f7b3e4a282b..81b55fe7b9f 100644 --- a/llvm/test/CodeGen/ARM/ret_arg4.ll +++ b/llvm/test/CodeGen/ARM/ret_arg4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { ret i32 %a4 diff --git a/llvm/test/CodeGen/ARM/ret_arg5.ll b/llvm/test/CodeGen/ARM/ret_arg5.ll index c4f9fb5e0a9..680e89f9aa4 100644 --- a/llvm/test/CodeGen/ARM/ret_arg5.ll +++ b/llvm/test/CodeGen/ARM/ret_arg5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) { ret i32 %a5 diff --git a/llvm/test/CodeGen/ARM/ret_f32_arg2.ll b/llvm/test/CodeGen/ARM/ret_f32_arg2.ll index 2bafea67553..0caee0bbaed 100644 --- a/llvm/test/CodeGen/ARM/ret_f32_arg2.ll +++ b/llvm/test/CodeGen/ARM/ret_f32_arg2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define float @test_f32(float %a1, float %a2) { ret float %a2 diff --git a/llvm/test/CodeGen/ARM/ret_f32_arg5.ll b/llvm/test/CodeGen/ARM/ret_f32_arg5.ll index c6ce60ecb9c..d39dc7e0526 100644 --- a/llvm/test/CodeGen/ARM/ret_f32_arg5.ll +++ b/llvm/test/CodeGen/ARM/ret_f32_arg5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define float @test_f32_arg5(float %a1, float %a2, float %a3, float %a4, float %a5) { ret float %a5 diff --git a/llvm/test/CodeGen/ARM/ret_f64_arg2.ll b/llvm/test/CodeGen/ARM/ret_f64_arg2.ll index 386e85f4b9a..c4519ff744c 100644 --- a/llvm/test/CodeGen/ARM/ret_f64_arg2.ll +++ b/llvm/test/CodeGen/ARM/ret_f64_arg2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define double @test_f64(double %a1, double %a2) { ret double %a2 diff --git a/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll b/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll index bdb0a606227..ef1125097b3 100644 --- a/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll +++ b/llvm/test/CodeGen/ARM/ret_f64_arg_reg_split.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=arm8 -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mcpu=arm8 -mattr=+vfp2 %s -o /dev/null define double @test_double_arg_reg_split(i32 %a1, double %a2) { ret double %a2 diff --git a/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll b/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll index 4f841a3cde7..113092050ff 100644 --- a/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll +++ b/llvm/test/CodeGen/ARM/ret_f64_arg_split.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define double @test_double_arg_split(i64 %a1, i32 %a2, double %a3) { ret double %a3 diff --git a/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll b/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll index 21443177d3d..f45923e7e8e 100644 --- a/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll +++ b/llvm/test/CodeGen/ARM/ret_f64_arg_stack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define double @test_double_arg_stack(i64 %a1, i32 %a2, i32 %a3, double %a4) { ret double %a4 diff --git a/llvm/test/CodeGen/ARM/ret_i128_arg2.ll b/llvm/test/CodeGen/ARM/ret_i128_arg2.ll index 908c34f8cda..a87f3f23b68 100644 --- a/llvm/test/CodeGen/ARM/ret_i128_arg2.ll +++ b/llvm/test/CodeGen/ARM/ret_i128_arg2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) { ret i128 %a3 diff --git a/llvm/test/CodeGen/ARM/ret_i64_arg2.ll b/llvm/test/CodeGen/ARM/ret_i64_arg2.ll index b1a1024acaf..c51d2b88a25 100644 --- a/llvm/test/CodeGen/ARM/ret_i64_arg2.ll +++ b/llvm/test/CodeGen/ARM/ret_i64_arg2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null define i64 @test_i64(i64 %a1, i64 %a2) { ret i64 %a2 diff --git a/llvm/test/CodeGen/ARM/ret_i64_arg3.ll b/llvm/test/CodeGen/ARM/ret_i64_arg3.ll index ffc1d2f4b52..602997ea360 100644 --- a/llvm/test/CodeGen/ARM/ret_i64_arg3.ll +++ b/llvm/test/CodeGen/ARM/ret_i64_arg3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) { ret i64 %a3 diff --git a/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll b/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll index 956bce558fc..0583b277f56 100644 --- a/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll +++ b/llvm/test/CodeGen/ARM/ret_i64_arg_split.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null define i64 @test_i64_arg_split(i64 %a1, i32 %a2, i64 %a3) { ret i64 %a3 diff --git a/llvm/test/CodeGen/ARM/ret_void.ll b/llvm/test/CodeGen/ARM/ret_void.ll index 2b7ae056288..93dc5c1f654 100644 --- a/llvm/test/CodeGen/ARM/ret_void.ll +++ b/llvm/test/CodeGen/ARM/ret_void.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null define void @test() { ret void diff --git a/llvm/test/CodeGen/ARM/rev.ll b/llvm/test/CodeGen/ARM/rev.ll index 6c380aee3d9..f95f97105b9 100644 --- a/llvm/test/CodeGen/ARM/rev.ll +++ b/llvm/test/CodeGen/ARM/rev.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s define i32 @test1(i32 %X) nounwind { ; CHECK: test1 diff --git a/llvm/test/CodeGen/ARM/sbfx.ll b/llvm/test/CodeGen/ARM/sbfx.ll index 36fbd1939c5..3c25edcaa75 100644 --- a/llvm/test/CodeGen/ARM/sbfx.ll +++ b/llvm/test/CodeGen/ARM/sbfx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s define i32 @f1(i32 %a) { entry: diff --git a/llvm/test/CodeGen/ARM/select-imm.ll b/llvm/test/CodeGen/ARM/select-imm.ll index 4dc297c7ec0..e2dc5542df0 100644 --- a/llvm/test/CodeGen/ARM/select-imm.ll +++ b/llvm/test/CodeGen/ARM/select-imm.ll @@ -1,8 +1,10 @@ -; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | \ -; RUN: FileCheck %s --check-prefix=ARMT2 -; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | \ -; RUN: FileCheck %s --check-prefix=THUMB2 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM + +; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ +; RUN: | FileCheck %s --check-prefix=ARMT2 + +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \ +; RUN: | FileCheck %s --check-prefix=THUMB2 define i32 @t1(i32 %c) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/ARM/select-undef.ll b/llvm/test/CodeGen/ARM/select-undef.ll index 23f7eb8b352..bae4d40d336 100644 --- a/llvm/test/CodeGen/ARM/select-undef.ll +++ b/llvm/test/CodeGen/ARM/select-undef.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs +; RUN: llc -mtriple=arm-eabi -mcpu=swift -verify-machineinstrs %s -o /dev/null + define i32 @func(i32 %arg0, i32 %arg1) { entry: %cmp = icmp slt i32 %arg0, 10 diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll index ed006d643f8..e9394a72073 100644 --- a/llvm/test/CodeGen/ARM/select.ll +++ b/llvm/test/CodeGen/ARM/select.ll @@ -1,6 +1,10 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP -; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON +; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s + +; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \ +; RUN: | FileCheck %s --check-prefix=CHECK-VFP + +; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+thumb2 %s -o - \ +; RUN: | FileCheck %s --check-prefix=CHECK-NEON define i32 @f1(i32 %a.s) { ;CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/ARM/setcc-sentinals.ll b/llvm/test/CodeGen/ARM/setcc-sentinals.ll index 1e0ea2f3ac7..dc45e0e1388 100644 --- a/llvm/test/CodeGen/ARM/setcc-sentinals.ll +++ b/llvm/test/CodeGen/ARM/setcc-sentinals.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -asm-verbose=false %s -o - | FileCheck %s define zeroext i1 @test0(i32 %x) nounwind { ; CHECK-LABEL: test0: diff --git a/llvm/test/CodeGen/ARM/smul.ll b/llvm/test/CodeGen/ARM/smul.ll index 686d791ce60..b7ddd10a568 100644 --- a/llvm/test/CodeGen/ARM/smul.ll +++ b/llvm/test/CodeGen/ARM/smul.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mcpu=generic -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=generic %s -o /dev/null +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s @x = weak global i16 0 ; <i16*> [#uses=1] @y = weak global i16 0 ; <i16*> [#uses=0] diff --git a/llvm/test/CodeGen/ARM/stack-frame.ll b/llvm/test/CodeGen/ARM/stack-frame.ll index 1dd57ddb9f2..a419074aa2c 100644 --- a/llvm/test/CodeGen/ARM/stack-frame.ll +++ b/llvm/test/CodeGen/ARM/stack-frame.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep add | count 1 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define void @f1() { %c = alloca i8, align 1 @@ -10,4 +9,6 @@ define i32 @f2() { ret i32 1 } +; CHECK: add +; CHECK-NOT: add diff --git a/llvm/test/CodeGen/ARM/str_post.ll b/llvm/test/CodeGen/ARM/str_post.ll index 32e3b856c03..a4f864065d5 100644 --- a/llvm/test/CodeGen/ARM/str_post.ll +++ b/llvm/test/CodeGen/ARM/str_post.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i16 @test1(i32* %X, i16* %A) { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/ARM/str_pre.ll b/llvm/test/CodeGen/ARM/str_pre.ll index d8b3f0e767b..60e6e9ecfeb 100644 --- a/llvm/test/CodeGen/ARM/str_pre.ll +++ b/llvm/test/CodeGen/ARM/str_pre.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep "str.*\!" | count 2 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define void @test1(i32* %X, i32* %A, i32** %dest) { %B = load i32* %A ; <i32> [#uses=1] @@ -16,3 +15,8 @@ define i16* @test2(i16* %X, i32* %A) { store i16 %tmp, i16* %Y ret i16* %Y } + +; CHECK: str{{.*}}! +; CHECK: str{{.*}}! +; CHECK-NOT: str{{.*}}! + diff --git a/llvm/test/CodeGen/ARM/str_trunc.ll b/llvm/test/CodeGen/ARM/str_trunc.ll index 2f1166b64b5..6739684d53b 100644 --- a/llvm/test/CodeGen/ARM/str_trunc.ll +++ b/llvm/test/CodeGen/ARM/str_trunc.ll @@ -1,7 +1,4 @@ -; RUN: llc < %s -march=arm | \ -; RUN: grep strb | count 1 -; RUN: llc < %s -march=arm | \ -; RUN: grep strh | count 1 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define void @test1(i32 %v, i16* %ptr) { %tmp = trunc i32 %v to i16 ; <i16> [#uses=1] @@ -14,3 +11,10 @@ define void @test2(i32 %v, i8* %ptr) { store i8 %tmp, i8* %ptr ret void } + +; CHECK: strh +; CHECK-NOT: strh + +; CHECK: strb +; CHECK-NOT: strb + diff --git a/llvm/test/CodeGen/ARM/sub.ll b/llvm/test/CodeGen/ARM/sub.ll index 7f82ca70126..67bde2a4e0a 100644 --- a/llvm/test/CodeGen/ARM/sub.ll +++ b/llvm/test/CodeGen/ARM/sub.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; 171 = 0x000000ab define i64 @f1(i64 %a) { diff --git a/llvm/test/CodeGen/ARM/sxt_rot.ll b/llvm/test/CodeGen/ARM/sxt_rot.ll index 656cd934fcf..5ddea2ec13d 100644 --- a/llvm/test/CodeGen/ARM/sxt_rot.ll +++ b/llvm/test/CodeGen/ARM/sxt_rot.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s define i32 @test0(i8 %A) { ; CHECK: test0 diff --git a/llvm/test/CodeGen/ARM/taildup-branch-weight.ll b/llvm/test/CodeGen/ARM/taildup-branch-weight.ll index 80bbc8c3238..0a16071a661 100644 --- a/llvm/test/CodeGen/ARM/taildup-branch-weight.ll +++ b/llvm/test/CodeGen/ARM/taildup-branch-weight.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=arm -print-machineinstrs=tailduplication -tail-dup-size=100 -enable-tail-merge=false -disable-cgp -o /dev/null 2>&1 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -print-machineinstrs=tailduplication -tail-dup-size=100 \ +; RUN: -enable-tail-merge=false -disable-cgp %s -o /dev/null 2>&1 \ +; RUN: | FileCheck %s ; CHECK: Machine code for function test0: ; CHECK: Successors according to CFG: BB#1(4) BB#2(124) diff --git a/llvm/test/CodeGen/ARM/trunc_ldr.ll b/llvm/test/CodeGen/ARM/trunc_ldr.ll index 3033c2ba3e2..2ce9b894d55 100644 --- a/llvm/test/CodeGen/ARM/trunc_ldr.ll +++ b/llvm/test/CodeGen/ARM/trunc_ldr.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep ldrb.*7 | count 1 -; RUN: llc < %s -march=arm | grep ldrsb.*7 | count 1 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** } %struct.B = type { float, float, i32, i32, i32, [0 x i8] } @@ -22,3 +21,10 @@ define i32 @f2(%struct.A* %d) { %tmp57 = sext i8 %tmp56 to i32 ret i32 %tmp57 } + +; CHECK: ldrb{{.*}}7 +; CHECK-NOT: ldrb{{.*}}7 + +; CHECK: ldrsb{{.*}}7 +; CHECK-NOT: ldrsb{{.*}}7 + diff --git a/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll b/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll index 5665440aa1d..360e3e13f59 100644 --- a/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/llvm/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr -; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov +; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s define void @bar(i8* %P, i16* %Q) { entry: @@ -16,3 +15,7 @@ entry: store i32 %tmp, i32* %P1, align 1 ret void } + +; CHECK-NOT: orr +; CHECK-NOT: mov + diff --git a/llvm/test/CodeGen/ARM/tst_teq.ll b/llvm/test/CodeGen/ARM/tst_teq.ll index c83111e6993..bac4fd91acf 100644 --- a/llvm/test/CodeGen/ARM/tst_teq.ll +++ b/llvm/test/CodeGen/ARM/tst_teq.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep tst -; RUN: llc < %s -march=arm | grep teq +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f(i32 %a) { entry: @@ -16,3 +15,7 @@ entry: %retval = select i1 %0, i32 20, i32 10 ; <i32> [#uses=1] ret i32 %retval } + +; CHECK: tst +; CHECK: teq + diff --git a/llvm/test/CodeGen/ARM/twoaddrinstr.ll b/llvm/test/CodeGen/ARM/twoaddrinstr.ll index 2172f6b9a6c..8da875fef27 100644 --- a/llvm/test/CodeGen/ARM/twoaddrinstr.ll +++ b/llvm/test/CodeGen/ARM/twoaddrinstr.ll @@ -1,5 +1,5 @@ ; Tests for the two-address instruction pass. -; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s define void @PR13378() nounwind { ; This was orriginally a crasher trying to schedule the instructions. diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store.ll b/llvm/test/CodeGen/ARM/unaligned_load_store.ll index e7ff63f8dbb..72163ae30c3 100644 --- a/llvm/test/CodeGen/ARM/unaligned_load_store.ll +++ b/llvm/test/CodeGen/ARM/unaligned_load_store.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -march=arm -pre-RA-sched=source | FileCheck %s -check-prefix=EXPANDED -; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source | FileCheck %s -check-prefix=EXPANDED -; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=UNALIGNED +; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source %s -o - \ +; RUN: | FileCheck %s -check-prefix=EXPANDED + +; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source %s -o - \ +; RUN: | FileCheck %s -check-prefix=EXPANDED + +; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 %s -o - \ +; RUN: | FileCheck %s -check-prefix=UNALIGNED ; rdar://7113725 ; rdar://12091029 diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll b/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll index 968a2c7ad0b..000ed489c4c 100644 --- a/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll +++ b/llvm/test/CodeGen/ARM/unaligned_load_store_vector.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=arm -mattr=+v7 -mattr=+neon | FileCheck %s +;RUN: llc -mtriple=arm-eabi -mattr=+v7 -mattr=+neon %s -o - | FileCheck %s ;ALIGN = 1 ;SIZE = 64 diff --git a/llvm/test/CodeGen/ARM/unord.ll b/llvm/test/CodeGen/ARM/unord.ll index bd28034b3ad..7243e9973fd 100644 --- a/llvm/test/CodeGen/ARM/unord.ll +++ b/llvm/test/CodeGen/ARM/unord.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep movne | count 1 -; RUN: llc < %s -march=arm | grep moveq | count 1 +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f1(float %X, float %Y) { %tmp = fcmp uno float %X, %Y @@ -12,3 +11,10 @@ define i32 @f2(float %X, float %Y) { %retval = select i1 %tmp, i32 1, i32 -1 ret i32 %retval } + +; CHECK: movne +; CHECK-NOT: movne + +; CHECK: moveq +; CHECK-NOT: moveq + diff --git a/llvm/test/CodeGen/ARM/uxt_rot.ll b/llvm/test/CodeGen/ARM/uxt_rot.ll index 628c0795d81..235416a35e6 100644 --- a/llvm/test/CodeGen/ARM/uxt_rot.ll +++ b/llvm/test/CodeGen/ARM/uxt_rot.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtb | count 1 -; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1 -; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1 +; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s define zeroext i8 @test1(i32 %A.u) { %B.u = trunc i32 %A.u to i8 @@ -22,3 +20,13 @@ define zeroext i32 @test3(i32 %A.u) { %F.u = zext i16 %E.u to i32 ret i32 %F.u } + +; CHECK: uxtb +; CHECK-NOT: uxtb + +; CHECK: uxtab +; CHECK-NOT: uxtab + +; CHECK: uxth +; CHECK-NOT: uxth + diff --git a/llvm/test/CodeGen/ARM/vaba.ll b/llvm/test/CodeGen/ARM/vaba.ll index 97139e9b6cc..6478b1843c6 100644 --- a/llvm/test/CodeGen/ARM/vaba.ll +++ b/llvm/test/CodeGen/ARM/vaba.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: vabas8: diff --git a/llvm/test/CodeGen/ARM/vabd.ll b/llvm/test/CodeGen/ARM/vabd.ll index 2eb6d935de8..9ba8be28c77 100644 --- a/llvm/test/CodeGen/ARM/vabd.ll +++ b/llvm/test/CodeGen/ARM/vabd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vabds8: diff --git a/llvm/test/CodeGen/ARM/vabs.ll b/llvm/test/CodeGen/ARM/vabs.ll index e8a81f8c654..3a1aec86edf 100644 --- a/llvm/test/CodeGen/ARM/vabs.ll +++ b/llvm/test/CodeGen/ARM/vabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vabss8: diff --git a/llvm/test/CodeGen/ARM/vadd.ll b/llvm/test/CodeGen/ARM/vadd.ll index fcb5408272f..86b0d029701 100644 --- a/llvm/test/CodeGen/ARM/vadd.ll +++ b/llvm/test/CodeGen/ARM/vadd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddi8: diff --git a/llvm/test/CodeGen/ARM/vargs.ll b/llvm/test/CodeGen/ARM/vargs.ll index 5f3536cbb9a..3b810f36cc7 100644 --- a/llvm/test/CodeGen/ARM/vargs.ll +++ b/llvm/test/CodeGen/ARM/vargs.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm +; RUN: llc -mtriple=arm-eabi %s -o /dev/null + @str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x i8]*> [#uses=1] define i32 @main() { diff --git a/llvm/test/CodeGen/ARM/vbits.ll b/llvm/test/CodeGen/ARM/vbits.ll index 7b48441958f..dfeaacf2085 100644 --- a/llvm/test/CodeGen/ARM/vbits.ll +++ b/llvm/test/CodeGen/ARM/vbits.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck %s define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: v_andi8: diff --git a/llvm/test/CodeGen/ARM/vbsl.ll b/llvm/test/CodeGen/ARM/vbsl.ll index 1e53e51f8bb..ddc37cc8244 100644 --- a/llvm/test/CodeGen/ARM/vbsl.ll +++ b/llvm/test/CodeGen/ARM/vbsl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; rdar://12471808 diff --git a/llvm/test/CodeGen/ARM/vceq.ll b/llvm/test/CodeGen/ARM/vceq.ll index 0a1f2ebe4f8..e3202e402cc 100644 --- a/llvm/test/CodeGen/ARM/vceq.ll +++ b/llvm/test/CodeGen/ARM/vceq.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vceqi8: diff --git a/llvm/test/CodeGen/ARM/vcge.ll b/llvm/test/CodeGen/ARM/vcge.ll index df72835ae20..3739f5ee8c5 100644 --- a/llvm/test/CodeGen/ARM/vcge.ll +++ b/llvm/test/CodeGen/ARM/vcge.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcges8: diff --git a/llvm/test/CodeGen/ARM/vcgt.ll b/llvm/test/CodeGen/ARM/vcgt.ll index adee76a2fbb..2f736f689ab 100644 --- a/llvm/test/CodeGen/ARM/vcgt.ll +++ b/llvm/test/CodeGen/ARM/vcgt.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vcgts8: diff --git a/llvm/test/CodeGen/ARM/vcnt.ll b/llvm/test/CodeGen/ARM/vcnt.ll index 0b539799833..390559b8280 100644 --- a/llvm/test/CodeGen/ARM/vcnt.ll +++ b/llvm/test/CodeGen/ARM/vcnt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; NB: this tests vcnt, vclz, and vcls define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { diff --git a/llvm/test/CodeGen/ARM/vcombine.ll b/llvm/test/CodeGen/ARM/vcombine.ll index 7885ac6245f..d611267fc7f 100644 --- a/llvm/test/CodeGen/ARM/vcombine.ll +++ b/llvm/test/CodeGen/ARM/vcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK: vcombine8 diff --git a/llvm/test/CodeGen/ARM/vcvt.ll b/llvm/test/CodeGen/ARM/vcvt.ll index 4f17dc55948..af4e6a3b046 100644 --- a/llvm/test/CodeGen/ARM/vcvt.ll +++ b/llvm/test/CodeGen/ARM/vcvt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fp16 %s -o - | FileCheck %s define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { ;CHECK-LABEL: vcvt_f32tos32: diff --git a/llvm/test/CodeGen/ARM/vdup.ll b/llvm/test/CodeGen/ARM/vdup.ll index db1a5163e5d..89f355c6875 100644 --- a/llvm/test/CodeGen/ARM/vdup.ll +++ b/llvm/test/CodeGen/ARM/vdup.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -verify-machineinstrs %s -o - \ +; RUN: | FileCheck %s define <8 x i8> @v_dup8(i8 %A) nounwind { ;CHECK-LABEL: v_dup8: diff --git a/llvm/test/CodeGen/ARM/vext.ll b/llvm/test/CodeGen/ARM/vext.ll index 5555a4759b0..4407451244e 100644 --- a/llvm/test/CodeGen/ARM/vext.ll +++ b/llvm/test/CodeGen/ARM/vext.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd: diff --git a/llvm/test/CodeGen/ARM/vfcmp.ll b/llvm/test/CodeGen/ARM/vfcmp.ll index a23db7be761..4b2fea9baa0 100644 --- a/llvm/test/CodeGen/ARM/vfcmp.ll +++ b/llvm/test/CodeGen/ARM/vfcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; This tests fcmp operations that do not map directly to NEON instructions. diff --git a/llvm/test/CodeGen/ARM/vhadd.ll b/llvm/test/CodeGen/ARM/vhadd.ll index 9c2ed579c98..6183db3702b 100644 --- a/llvm/test/CodeGen/ARM/vhadd.ll +++ b/llvm/test/CodeGen/ARM/vhadd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhadds8: diff --git a/llvm/test/CodeGen/ARM/vhsub.ll b/llvm/test/CodeGen/ARM/vhsub.ll index 4bc2e87ab57..f1a0cb27f57 100644 --- a/llvm/test/CodeGen/ARM/vhsub.ll +++ b/llvm/test/CodeGen/ARM/vhsub.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vhsubs8: diff --git a/llvm/test/CodeGen/ARM/vicmp.ll b/llvm/test/CodeGen/ARM/vicmp.ll index 0a8f103102b..bebb32062f7 100644 --- a/llvm/test/CodeGen/ARM/vicmp.ll +++ b/llvm/test/CodeGen/ARM/vicmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s ; This tests icmp operations that do not map directly to NEON instructions. ; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult) diff --git a/llvm/test/CodeGen/ARM/vld1.ll b/llvm/test/CodeGen/ARM/vld1.ll index 49bc84df6e1..caeeada90ff 100644 --- a/llvm/test/CodeGen/ARM/vld1.ll +++ b/llvm/test/CodeGen/ARM/vld1.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s + +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \ +; RUN: | FileCheck %s define <8 x i8> @vld1i8(i8* %A) nounwind { ;CHECK-LABEL: vld1i8: diff --git a/llvm/test/CodeGen/ARM/vld2.ll b/llvm/test/CodeGen/ARM/vld2.ll index fddafeab91c..7ac5cc709b3 100644 --- a/llvm/test/CodeGen/ARM/vld2.ll +++ b/llvm/test/CodeGen/ARM/vld2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> } diff --git a/llvm/test/CodeGen/ARM/vld3.ll b/llvm/test/CodeGen/ARM/vld3.ll index d6eb4c2f6dd..171a03c24da 100644 --- a/llvm/test/CodeGen/ARM/vld3.ll +++ b/llvm/test/CodeGen/ARM/vld3.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o -| FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } diff --git a/llvm/test/CodeGen/ARM/vld4.ll b/llvm/test/CodeGen/ARM/vld4.ll index ff162bb022e..94ad143ae0f 100644 --- a/llvm/test/CodeGen/ARM/vld4.ll +++ b/llvm/test/CodeGen/ARM/vld4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } diff --git a/llvm/test/CodeGen/ARM/vlddup.ll b/llvm/test/CodeGen/ARM/vlddup.ll index f5339f8495a..64aac562c1e 100644 --- a/llvm/test/CodeGen/ARM/vlddup.ll +++ b/llvm/test/CodeGen/ARM/vlddup.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vld1dupi8(i8* %A) nounwind { ;CHECK-LABEL: vld1dupi8: diff --git a/llvm/test/CodeGen/ARM/vldlane.ll b/llvm/test/CodeGen/ARM/vldlane.ll index e16746ce937..c7d69ff9780 100644 --- a/llvm/test/CodeGen/ARM/vldlane.ll +++ b/llvm/test/CodeGen/ARM/vldlane.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s -; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s + +; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \ +; RUN: | FileCheck %s define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vld1lanei8: diff --git a/llvm/test/CodeGen/ARM/vminmax.ll b/llvm/test/CodeGen/ARM/vminmax.ll index 81f45782a96..1167ebe0671 100644 --- a/llvm/test/CodeGen/ARM/vminmax.ll +++ b/llvm/test/CodeGen/ARM/vminmax.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmins8: diff --git a/llvm/test/CodeGen/ARM/vmla.ll b/llvm/test/CodeGen/ARM/vmla.ll index caf655609c2..6073fc5566f 100644 --- a/llvm/test/CodeGen/ARM/vmla.ll +++ b/llvm/test/CodeGen/ARM/vmla.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { ;CHECK-LABEL: vmlai8: diff --git a/llvm/test/CodeGen/ARM/vmls.ll b/llvm/test/CodeGen/ARM/vmls.ll index 61f3424909e..f86739cea3f 100644 --- a/llvm/test/CodeGen/ARM/vmls.ll +++ b/llvm/test/CodeGen/ARM/vmls.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { ;CHECK-LABEL: vmlsi8: diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll index 8b63138bda8..7900af44ef0 100644 --- a/llvm/test/CodeGen/ARM/vmov.ll +++ b/llvm/test/CodeGen/ARM/vmov.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @v_movi8() nounwind { ;CHECK-LABEL: v_movi8: diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll index de329acdf3c..0fa43d801bb 100644 --- a/llvm/test/CodeGen/ARM/vmul.ll +++ b/llvm/test/CodeGen/ARM/vmul.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vmuli8: diff --git a/llvm/test/CodeGen/ARM/vneg.ll b/llvm/test/CodeGen/ARM/vneg.ll index 1be4f748213..4d548ddf814 100644 --- a/llvm/test/CodeGen/ARM/vneg.ll +++ b/llvm/test/CodeGen/ARM/vneg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vnegs8: diff --git a/llvm/test/CodeGen/ARM/vpadal.ll b/llvm/test/CodeGen/ARM/vpadal.ll index a616a8d270a..ffeac737fa3 100644 --- a/llvm/test/CodeGen/ARM/vpadal.ll +++ b/llvm/test/CodeGen/ARM/vpadal.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpadals8: diff --git a/llvm/test/CodeGen/ARM/vpadd.ll b/llvm/test/CodeGen/ARM/vpadd.ll index ecaabd3b9f7..01cb1c74e38 100644 --- a/llvm/test/CodeGen/ARM/vpadd.ll +++ b/llvm/test/CodeGen/ARM/vpadd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpaddi8: diff --git a/llvm/test/CodeGen/ARM/vpminmax.ll b/llvm/test/CodeGen/ARM/vpminmax.ll index c68b3193c19..0b893e5bc89 100644 --- a/llvm/test/CodeGen/ARM/vpminmax.ll +++ b/llvm/test/CodeGen/ARM/vpminmax.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vpmins8: diff --git a/llvm/test/CodeGen/ARM/vqadd.ll b/llvm/test/CodeGen/ARM/vqadd.ll index 78407668546..81acc8bc5ab 100644 --- a/llvm/test/CodeGen/ARM/vqadd.ll +++ b/llvm/test/CodeGen/ARM/vqadd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqadds8: diff --git a/llvm/test/CodeGen/ARM/vqshl.ll b/llvm/test/CodeGen/ARM/vqshl.ll index b5cd71613d4..4afef6dbd65 100644 --- a/llvm/test/CodeGen/ARM/vqshl.ll +++ b/llvm/test/CodeGen/ARM/vqshl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqshls8: diff --git a/llvm/test/CodeGen/ARM/vqshrn.ll b/llvm/test/CodeGen/ARM/vqshrn.ll index 4abae700f87..f02482c0f77 100644 --- a/llvm/test/CodeGen/ARM/vqshrn.ll +++ b/llvm/test/CodeGen/ARM/vqshrn.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vqshrns8: diff --git a/llvm/test/CodeGen/ARM/vqsub.ll b/llvm/test/CodeGen/ARM/vqsub.ll index 90bc3492fc5..4af43801920 100644 --- a/llvm/test/CodeGen/ARM/vqsub.ll +++ b/llvm/test/CodeGen/ARM/vqsub.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vqsubs8: diff --git a/llvm/test/CodeGen/ARM/vrec.ll b/llvm/test/CodeGen/ARM/vrec.ll index c0deca99576..91979e5a334 100644 --- a/llvm/test/CodeGen/ARM/vrec.ll +++ b/llvm/test/CodeGen/ARM/vrec.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vrecpei32: diff --git a/llvm/test/CodeGen/ARM/vrev.ll b/llvm/test/CodeGen/ARM/vrev.ll index b6da694e180..eb76ba6ea08 100644 --- a/llvm/test/CodeGen/ARM/vrev.ll +++ b/llvm/test/CodeGen/ARM/vrev.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64D8: diff --git a/llvm/test/CodeGen/ARM/vselect_imax.ll b/llvm/test/CodeGen/ARM/vselect_imax.ll index 9ea56a47bd2..e999034fa47 100644 --- a/llvm/test/CodeGen/ARM/vselect_imax.ll +++ b/llvm/test/CodeGen/ARM/vselect_imax.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s ; Make sure that ARM backend with NEON handles vselect. define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { diff --git a/llvm/test/CodeGen/ARM/vshift.ll b/llvm/test/CodeGen/ARM/vshift.ll index 92a5ebd0008..618a137b5b0 100644 --- a/llvm/test/CodeGen/ARM/vshift.ll +++ b/llvm/test/CodeGen/ARM/vshift.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vshls8: diff --git a/llvm/test/CodeGen/ARM/vshiftins.ll b/llvm/test/CodeGen/ARM/vshiftins.ll index 27610bfa677..9526c322201 100644 --- a/llvm/test/CodeGen/ARM/vshiftins.ll +++ b/llvm/test/CodeGen/ARM/vshiftins.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsli8: diff --git a/llvm/test/CodeGen/ARM/vshl.ll b/llvm/test/CodeGen/ARM/vshl.ll index 462f7fe7fb0..6228652fc71 100644 --- a/llvm/test/CodeGen/ARM/vshl.ll +++ b/llvm/test/CodeGen/ARM/vshl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vshls8: diff --git a/llvm/test/CodeGen/ARM/vshll.ll b/llvm/test/CodeGen/ARM/vshll.ll index 8faee118ff2..27873eb7275 100644 --- a/llvm/test/CodeGen/ARM/vshll.ll +++ b/llvm/test/CodeGen/ARM/vshll.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vshlls8: diff --git a/llvm/test/CodeGen/ARM/vshrn.ll b/llvm/test/CodeGen/ARM/vshrn.ll index cc936be8292..8aa009ab823 100644 --- a/llvm/test/CodeGen/ARM/vshrn.ll +++ b/llvm/test/CodeGen/ARM/vshrn.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vshrns8: diff --git a/llvm/test/CodeGen/ARM/vsra.ll b/llvm/test/CodeGen/ARM/vsra.ll index 652410e7c4e..fa5985a330c 100644 --- a/llvm/test/CodeGen/ARM/vsra.ll +++ b/llvm/test/CodeGen/ARM/vsra.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsras8: diff --git a/llvm/test/CodeGen/ARM/vst1.ll b/llvm/test/CodeGen/ARM/vst1.ll index 36439fd7adf..14f3ff06630 100644 --- a/llvm/test/CodeGen/ARM/vst1.ll +++ b/llvm/test/CodeGen/ARM/vst1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1i8: diff --git a/llvm/test/CodeGen/ARM/vst2.ll b/llvm/test/CodeGen/ARM/vst2.ll index 7551a562cf0..2180259d57f 100644 --- a/llvm/test/CodeGen/ARM/vst2.ll +++ b/llvm/test/CodeGen/ARM/vst2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst2i8: diff --git a/llvm/test/CodeGen/ARM/vst3.ll b/llvm/test/CodeGen/ARM/vst3.ll index 65625de3457..5f150edf31d 100644 --- a/llvm/test/CodeGen/ARM/vst3.ll +++ b/llvm/test/CodeGen/ARM/vst3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon -fast-isel=0 -O0 %s -o - | FileCheck %s define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst3i8: diff --git a/llvm/test/CodeGen/ARM/vst4.ll b/llvm/test/CodeGen/ARM/vst4.ll index 83a6c704865..44c76b5ed18 100644 --- a/llvm/test/CodeGen/ARM/vst4.ll +++ b/llvm/test/CodeGen/ARM/vst4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst4i8: diff --git a/llvm/test/CodeGen/ARM/vstlane.ll b/llvm/test/CodeGen/ARM/vstlane.ll index 34c5c70fffa..7dd6e7b439e 100644 --- a/llvm/test/CodeGen/ARM/vstlane.ll +++ b/llvm/test/CodeGen/ARM/vstlane.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8: diff --git a/llvm/test/CodeGen/ARM/vsub.ll b/llvm/test/CodeGen/ARM/vsub.ll index 6b95b97378e..d1a094b9275 100644 --- a/llvm/test/CodeGen/ARM/vsub.ll +++ b/llvm/test/CodeGen/ARM/vsub.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsubi8: diff --git a/llvm/test/CodeGen/ARM/vtbl.ll b/llvm/test/CodeGen/ARM/vtbl.ll index 21614b044f9..32258a30da9 100644 --- a/llvm/test/CodeGen/ARM/vtbl.ll +++ b/llvm/test/CodeGen/ARM/vtbl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } diff --git a/llvm/test/CodeGen/ARM/vtrn.ll b/llvm/test/CodeGen/ARM/vtrn.ll index 7d101bc6195..cdae7f8ec37 100644 --- a/llvm/test/CodeGen/ARM/vtrn.ll +++ b/llvm/test/CodeGen/ARM/vtrn.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vtrni8: diff --git a/llvm/test/CodeGen/ARM/vuzp.ll b/llvm/test/CodeGen/ARM/vuzp.ll index 2d193c11419..832be6c3daf 100644 --- a/llvm/test/CodeGen/ARM/vuzp.ll +++ b/llvm/test/CodeGen/ARM/vuzp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vuzpi8: diff --git a/llvm/test/CodeGen/ARM/vzip.ll b/llvm/test/CodeGen/ARM/vzip.ll index f71aef7ef13..f74dc62599c 100644 --- a/llvm/test/CodeGen/ARM/vzip.ll +++ b/llvm/test/CodeGen/ARM/vzip.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vzipi8: diff --git a/llvm/test/CodeGen/ARM/weak.ll b/llvm/test/CodeGen/ARM/weak.ll index 5ac4b8c061d..375ce22127a 100644 --- a/llvm/test/CodeGen/ARM/weak.ll +++ b/llvm/test/CodeGen/ARM/weak.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm | grep .weak.*f -; RUN: llc < %s -march=arm | grep .weak.*h +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define weak i32 @f() { entry: @@ -14,3 +13,6 @@ entry: declare extern_weak void @h() +; CHECK: {{.}}weak{{.*}}f +; CHECK: {{.}}weak{{.*}}h + diff --git a/llvm/test/CodeGen/ARM/weak2.ll b/llvm/test/CodeGen/ARM/weak2.ll index cf327bbf5c8..82ab90efb11 100644 --- a/llvm/test/CodeGen/ARM/weak2.ll +++ b/llvm/test/CodeGen/ARM/weak2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep .weak +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s define i32 @f(i32 %a) { entry: @@ -16,3 +16,6 @@ UnifiedReturnBlock: ; preds = %entry } declare extern_weak i32 @test_weak(...) + +; CHECK: {{.}}weak + diff --git a/llvm/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s b/llvm/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s index 172abcf6f81..66fba3b6ac9 100644 --- a/llvm/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s +++ b/llvm/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s @@ -1,5 +1,6 @@ -@ RUN: llvm-mc -arch arm %s +@ RUN: llvm-mc -triple arm-eabi %s -o - | FileCheck %s + @ CHECK: test: -@ CHECK: br r1 +@ CHECK: bl r1 test: bl r1 diff --git a/llvm/test/MC/ARM/arm-ldrd.s b/llvm/test/MC/ARM/arm-ldrd.s index c26ee25aad7..af4bc735f39 100644 --- a/llvm/test/MC/ARM/arm-ldrd.s +++ b/llvm/test/MC/ARM/arm-ldrd.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -arch arm -mattr=+v5te %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple arm-eabi -mattr=+v5te %s -o /dev/null 2>&1 | FileCheck %s // // rdar://14479793 diff --git a/llvm/test/MC/ARM/thumb2-ldrd.s b/llvm/test/MC/ARM/thumb2-ldrd.s index 4463c21fe8c..5166ff00ec1 100644 --- a/llvm/test/MC/ARM/thumb2-ldrd.s +++ b/llvm/test/MC/ARM/thumb2-ldrd.s @@ -1,9 +1,16 @@ -// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \ -// RUN: < %s >/dev/null 2> %t -// RUN: grep "error: destination operands can't be identical" %t | count 4 -// rdar://14479780 +@ RUN: not llvm-mc -triple thumb-eabi -mattr=+thumb2 %s -o /dev/null 2>&1 \ +@ RUN: | FileCheck %s + +@ rdar://14479780 ldrd r0, r0, [pc, #0] ldrd r0, r0, [r1, #4] ldrd r0, r0, [r1], #4 ldrd r0, r0, [r1, #4]! + +@ CHECK: error: destination operands can't be identical +@ CHECK: error: destination operands can't be identical +@ CHECK: error: destination operands can't be identical +@ CHECK: error: destination operands can't be identical +@ CHECK-NOT: error: destination operands can't be identical + |
