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| author | Sanjay Patel <spatel@rotateright.com> | 2019-03-14 19:22:00 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-03-14 19:22:00 +0000 |
| commit | 6e86216531e2c53f171aaf8b911327ab616c6c0d (patch) | |
| tree | 3f93c39c48b99db1b07e1c3c583b922c934ea514 | |
| parent | bb26a7eb113c5a013f4e5d40f72846194dadefeb (diff) | |
| download | bcm5719-llvm-6e86216531e2c53f171aaf8b911327ab616c6c0d.tar.gz bcm5719-llvm-6e86216531e2c53f171aaf8b911327ab616c6c0d.zip | |
[InstCombine] add tests for funnel shift constant shift amount mod bitwidth; NFC
llvm-svn: 356191
| -rw-r--r-- | llvm/test/Transforms/InstCombine/fsh.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/fsh.ll b/llvm/test/Transforms/InstCombine/fsh.ll index 6c1dc2f20b7..eaa699cd342 100644 --- a/llvm/test/Transforms/InstCombine/fsh.ll +++ b/llvm/test/Transforms/InstCombine/fsh.ll @@ -344,6 +344,42 @@ define <2 x i31> @fshl_constant_shift_amount_modulo_bitwidth_vec(<2 x i31> %x, < ret <2 x i31> %r } +define i32 @fshl_constant_shift_amount_modulo_bitwidth(i32 %x, i32 %y) { +; CHECK-LABEL: @fshl_constant_shift_amount_modulo_bitwidth( +; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 33) +; CHECK-NEXT: ret i32 [[R]] +; + %r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 33) + ret i32 %r +} + +define i33 @fshr_constant_shift_amount_modulo_bitwidth(i33 %x, i33 %y) { +; CHECK-LABEL: @fshr_constant_shift_amount_modulo_bitwidth( +; CHECK-NEXT: [[R:%.*]] = call i33 @llvm.fshr.i33(i33 [[X:%.*]], i33 [[Y:%.*]], i33 34) +; CHECK-NEXT: ret i33 [[R]] +; + %r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 34) + ret i33 %r +} + +define <2 x i32> @fshr_constant_shift_amount_modulo_bitwidth_vec(<2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @fshr_constant_shift_amount_modulo_bitwidth_vec( +; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> <i32 34, i32 -1>) +; CHECK-NEXT: ret <2 x i32> [[R]] +; + %r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 34, i32 -1>) + ret <2 x i32> %r +} + +define <2 x i31> @fshl_constant_shift_amount_modulo_bitwidth_vec(<2 x i31> %x, <2 x i31> %y) { +; CHECK-LABEL: @fshl_constant_shift_amount_modulo_bitwidth_vec( +; CHECK-NEXT: [[R:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[X:%.*]], <2 x i31> [[Y:%.*]], <2 x i31> <i31 34, i31 -1>) +; CHECK-NEXT: ret <2 x i31> [[R]] +; + %r = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %x, <2 x i31> %y, <2 x i31> <i31 34, i31 -1>) + ret <2 x i31> %r +} + ; The shift modulo bitwidth is the same for all vector elements, but this is not simplified yet. define <2 x i31> @fshl_only_op1_demanded_vec_nonsplat(<2 x i31> %x, <2 x i31> %y) { ; CHECK-LABEL: @fshl_only_op1_demanded_vec_nonsplat( |
