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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-14 04:03:18 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-02-14 04:03:18 +0000 |
| commit | 6e26b8d8541357e53d04f90ba8bc9635e5fe1004 (patch) | |
| tree | 0b440942835248cd51d95454be77d72f3c2bc128 | |
| parent | 35733e2dec87f6430ec7cfc7b8680e19fd147c82 (diff) | |
| download | bcm5719-llvm-6e26b8d8541357e53d04f90ba8bc9635e5fe1004.tar.gz bcm5719-llvm-6e26b8d8541357e53d04f90ba8bc9635e5fe1004.zip | |
R600/SI: Fix schedule model for v_div_scale_{f32|f64}
llvm-svn: 229235
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 9ec79945b7a..032d6c2abfc 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1735,9 +1735,11 @@ defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", } // isCommutable = 1, SchedRW = [WriteQuarterRate32] +let SchedRW = [WriteFloatFMA, WriteSALU] in { defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d, 0x1e0>, "v_div_scale_f32", []>; +} -let SchedRW = [WriteDouble] in { +let SchedRW = [WriteDouble, WriteSALU] in { // Double precision division pre-scale. defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e, 0x1e1>, "v_div_scale_f64", []>; } // let SchedRW = [WriteDouble] |
