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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-15 23:37:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-15 23:37:42 +0000 |
| commit | 6de7af424216fb153de2096c16a3e573b6be483a (patch) | |
| tree | 8088f501413fe8f9c0c818e4db09872be4fc8861 | |
| parent | 6909b5b567a4fa68c5be1ee6af2609b929eb8512 (diff) | |
| download | bcm5719-llvm-6de7af424216fb153de2096c16a3e573b6be483a.tar.gz bcm5719-llvm-6de7af424216fb153de2096c16a3e573b6be483a.zip | |
Move variable down to use
llvm-svn: 219867
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index fa384db230b..b7df3d8341d 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -2160,10 +2160,6 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N, WidthVal); } - APInt Demanded = APInt::getBitsSet(32, - OffsetVal, - OffsetVal + WidthVal); - if ((OffsetVal + WidthVal) >= 32) { SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32); return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, @@ -2171,6 +2167,10 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N, } if (BitsFrom.hasOneUse()) { + APInt Demanded = APInt::getBitsSet(32, + OffsetVal, + OffsetVal + WidthVal); + APInt KnownZero, KnownOne; TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), !DCI.isBeforeLegalizeOps()); |

