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| author | Craig Topper <craig.topper@intel.com> | 2019-05-22 19:51:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-05-22 19:51:48 +0000 |
| commit | 6dbf4a86a7c8d2a63aebb96c3e7d1ac477a40d9e (patch) | |
| tree | 23c87ae8fdc58ef092e186b5845704d9f6078558 | |
| parent | 2f1895e03d9ee89f247c8830dcabaf6060d73c74 (diff) | |
| download | bcm5719-llvm-6dbf4a86a7c8d2a63aebb96c3e7d1ac477a40d9e.tar.gz bcm5719-llvm-6dbf4a86a7c8d2a63aebb96c3e7d1ac477a40d9e.zip | |
[X86] Add more icelake model numbers to compiler-rt implementation of __builtin_cpu_is.
Using model numbers found in Table 2-1 of the May 2019 version
of the Intel Software Developer's Manual Volume 4.
llvm-svn: 361423
| -rw-r--r-- | compiler-rt/lib/builtins/cpu_model.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/compiler-rt/lib/builtins/cpu_model.c b/compiler-rt/lib/builtins/cpu_model.c index 1290d4ce843..f953aed959e 100644 --- a/compiler-rt/lib/builtins/cpu_model.c +++ b/compiler-rt/lib/builtins/cpu_model.c @@ -363,11 +363,19 @@ static void getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, break; // Icelake: + case 0x7d: case 0x7e: *Type = INTEL_COREI7; *Subtype = INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client" break; + // Icelake Xeon: + case 0x6a: + case 0x6c: + *Type = INTEL_COREI7; + *Subtype = INTEL_COREI7_ICELAKE_SERVER; // "icelake-server" + break; + case 0x1c: // Most 45 nm Intel Atom processors case 0x26: // 45 nm Atom Lincroft case 0x27: // 32 nm Atom Medfield |
