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authorTom Stellard <thomas.stellard@amd.com>2016-10-21 20:25:11 +0000
committerTom Stellard <thomas.stellard@amd.com>2016-10-21 20:25:11 +0000
commit6c7dd980e4eb68da22abaae5ac749a6b3e465969 (patch)
treec038e4b9258d2a10f0c9e3a201ca3c03afbbb079
parentca92c36e014bc806458c0a75e039881030e885e6 (diff)
downloadbcm5719-llvm-6c7dd980e4eb68da22abaae5ac749a6b3e465969.tar.gz
bcm5719-llvm-6c7dd980e4eb68da22abaae5ac749a6b3e465969.zip
AMDGPU/SI: Fix crash caused by r284267
Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25782 llvm-svn: 284875
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp5
-rw-r--r--llvm/test/CodeGen/AMDGPU/mul_int24.ll25
2 files changed, 28 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index ac6c7e33fb3..a7fd748e85d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -2631,8 +2631,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
case AMDGPUISD::MUL_U24:
case AMDGPUISD::MULHI_I24:
case AMDGPUISD::MULHI_U24: {
- simplifyI24(N, 0, DCI);
- simplifyI24(N, 1, DCI);
+ // If the first call to simplify is successfull, then N may end up being
+ // deleted, so we shouldn't call simplifyI24 again.
+ simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI);
return SDValue();
}
case AMDGPUISD::MUL_LOHI_I24:
diff --git a/llvm/test/CodeGen/AMDGPU/mul_int24.ll b/llvm/test/CodeGen/AMDGPU/mul_int24.ll
index 4503e86209b..0beb9524ed7 100644
--- a/llvm/test/CodeGen/AMDGPU/mul_int24.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul_int24.ll
@@ -146,4 +146,29 @@ entry:
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
+
+; GCN-LABEL: {{^}}simplify_i24_crash:
+; GCN: v_mul_i32_i24_e32 v[[VAL_LO:[0-9]+]]
+; GCN: v_mov_b32_e32 v[[VAL_HI:[0-9]+]], v[[VAL_LO]]
+; GCN: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
+define void @simplify_i24_crash(<2 x i32> addrspace(1)* %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {
+bb:
+ %cmp = icmp eq i32 %arg0, 0
+ br i1 %cmp, label %bb11, label %bb7
+
+bb11:
+ %tmp14 = shufflevector <2 x i32> %arg1, <2 x i32> undef, <2 x i32> zeroinitializer
+ %tmp16 = shufflevector <2 x i32> %arg2, <2 x i32> undef, <2 x i32> zeroinitializer
+ %tmp17 = shl <2 x i32> %tmp14, <i32 8, i32 8>
+ %tmp18 = ashr <2 x i32> %tmp17, <i32 8, i32 8>
+ %tmp19 = shl <2 x i32> %tmp16, <i32 8, i32 8>
+ %tmp20 = ashr <2 x i32> %tmp19, <i32 8, i32 8>
+ %tmp21 = mul <2 x i32> %tmp18, %tmp20
+ store <2 x i32> %tmp21, <2 x i32> addrspace(1)* %out
+ br label %bb7
+
+bb7:
+ ret void
+
+}
attributes #0 = { nounwind }
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