summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJohnny Chen <johnny.chen@apple.com>2012-05-22 19:41:53 +0000
committerJohnny Chen <johnny.chen@apple.com>2012-05-22 19:41:53 +0000
commit6c26f0b2a7ee3a74fac538c38453ecc581bd0536 (patch)
tree15f14f586073e1822b8e4b4c547c66c34be6e023
parent819b35daf77d5114951eb9758cb8da157ff7d91e (diff)
downloadbcm5719-llvm-6c26f0b2a7ee3a74fac538c38453ecc581bd0536.tar.gz
bcm5719-llvm-6c26f0b2a7ee3a74fac538c38453ecc581bd0536.zip
Fix a typo.
llvm-svn: 157278
-rw-r--r--lldb/test/functionalities/register/TestRegisters.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/lldb/test/functionalities/register/TestRegisters.py b/lldb/test/functionalities/register/TestRegisters.py
index 551a16baa9b..2ac6861247b 100644
--- a/lldb/test/functionalities/register/TestRegisters.py
+++ b/lldb/test/functionalities/register/TestRegisters.py
@@ -74,7 +74,7 @@ class RegisterCommandsTestCase(TestBase):
# Test reading of rax and eax.
self.runCmd("register read rax eax")
- # No write rax with a unique bit pattern and test that eax indeed represents the lower half of rax.
+ # Now write rax with a unique bit pattern and test that eax indeed represents the lower half of rax.
self.runCmd("register write rax 0x1234567887654321")
self.expect("expr -- ($rax & 0xffffffff) == $eax",
substrs = ['true'])
OpenPOWER on IntegriCloud