Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

10 files changed, 46 insertions, 45 deletions

diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 3ce360bce74..3f1cdd27ca3 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -400,7 +400,7 @@ def SUBREG_TO_REG : Instruction {
   let Namespace = "TargetInstrInfo";
   let neverHasSideEffects = 1;
 }
-def COPY_TO_SUBCLASS : Instruction {
+def COPY_TO_REGCLASS : Instruction {
   let OutOperandList = (ops unknown:$dst);
   let InOperandList = (ops unknown:$src, i32imm:$regclass);
   let AsmString = "";
diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h
index fb41e4d3e55..c6b89878bdc 100644
--- a/llvm/include/llvm/Target/TargetInstrInfo.h
+++ b/llvm/include/llvm/Target/TargetInstrInfo.h
@@ -75,12 +75,14 @@ public:
     /// zext from i32 to i64 via implicit zero-extension).
     SUBREG_TO_REG = 9,
 
-    /// COPY_TO_SUBCLASS - This instruction is a placeholder for a plain
+    /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
     /// register-to-register copy into a specific register class. This is only
     /// used between instruction selection and MachineInstr creation, before
-    /// virtual registers have been created for all the instructions. As with
-    /// normal copies, these may be optimized away by the coalescer.
-    COPY_TO_SUBCLASS = 10
+    /// virtual registers have been created for all the instructions, and it's
+    /// only needed in cases where the register classes implied by the
+    /// instructions are insufficient. The actual MachineInstrs to perform
+    /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
+    COPY_TO_REGCLASS = 10
   };
 
   unsigned getNumOpcodes() const { return NumOpcodes; }
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index cd969dc7333..2a278b749a8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -134,10 +134,10 @@ namespace llvm {
     void EmitSubregNode(SDNode *Node, 
                         DenseMap<SDValue, unsigned> &VRBaseMap);
 
-    /// EmitCopyToSubclassNode - Generate machine code for COPY_TO_SUBCLASS
+    /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS
     /// nodes.
     ///
-    void EmitCopyToSubclassNode(SDNode *Node,
+    void EmitCopyToRegClassNode(SDNode *Node,
                                 DenseMap<SDValue, unsigned> &VRBaseMap);
 
     /// getVR - Return the virtual register corresponding to the specified result
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 084ecb75550..94333d34454 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -464,12 +464,12 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
   assert(isNew && "Node emitted out of order - early");
 }
 
-/// EmitCopyToSubclassNode - Generate machine code for COPY_TO_SUBCLASS nodes.
-/// COPY_TO_SUBCLASS is just a normal copy, except that the destination
+/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
+/// COPY_TO_REGCLASS is just a normal copy, except that the destination
 /// register is constrained to be in a particular register class.
 ///
 void
-ScheduleDAGSDNodes::EmitCopyToSubclassNode(SDNode *Node,
+ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
   const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
@@ -477,19 +477,18 @@ ScheduleDAGSDNodes::EmitCopyToSubclassNode(SDNode *Node,
   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
   const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
 
-  assert(SrcRC->hasSubClass(DstRC) &&
-         "COPY_TO_SUBCLASS destination class is not a proper subclass!");
-
   // Create the new VReg in the destination class and emit a copy.
   unsigned NewVReg = MRI.createVirtualRegister(DstRC);
   bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
                                    DstRC, SrcRC);
-  // If the target didn't handle that, emit a plain copy.
-  if (!Emitted)
+  // If the target didn't handle the copy with different register
+  // classes and the destination is a subset of the source,
+  // try a normal same-RC copy.
+  if (!Emitted && SrcRC->hasSubClass(DstRC))
     Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
                                 SrcRC, SrcRC);
   assert(Emitted &&
-         "Unable to issue a copy instruction for a COPY_TO_SUBCLASS node!\n");
+         "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
 
   SDValue Op(Node, 0);
   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
@@ -513,9 +512,9 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
       return;
     }
 
-    // Handle COPY_TO_SUBCLASS specially.
-    if (Opc == TargetInstrInfo::COPY_TO_SUBCLASS) {
-      EmitCopyToSubclassNode(Node, VRBaseMap);
+    // Handle COPY_TO_REGCLASS specially.
+    if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
+      EmitCopyToRegClassNode(Node, VRBaseMap);
       return;
     }
 
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td
index 05bccabc304..1785bd13316 100644
--- a/llvm/lib/Target/X86/X86Instr64bit.td
+++ b/llvm/lib/Target/X86/X86Instr64bit.td
@@ -1578,18 +1578,18 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
           (SUBREG_TO_REG
             (i64 0),
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR64:$src, GR64_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
                               x86_subreg_8bit_hi)),
             x86_subreg_32bit)>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
           (MOVZX32_NOREXrr8
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32_NOREXrr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In64BitMode]>;
@@ -1598,18 +1598,18 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR64:$src, GR64_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
                             x86_subreg_8bit_hi))>;
 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
           (MOV8mr_NOREX
             addr:$dst,
-            (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
 
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 830796e3a38..077b4563b06 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -3349,12 +3349,12 @@ def : Pat<(and GR32:$src1, 0xffff),
           (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR32:$src1, 0xff),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src1, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 // r & (2^8-1) ==> movz
 def : Pat<(and GR16:$src1, 0xff),
-          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src1, GR16_),
+          (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3362,11 +3362,11 @@ def : Pat<(and GR16:$src1, 0xff),
 def : Pat<(sext_inreg GR32:$src, i16),
           (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
 def : Pat<(sext_inreg GR32:$src, i8),
-          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 def : Pat<(sext_inreg GR16:$src, i8),
-          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                                       x86_subreg_8bit))>,
       Requires<[In32BitMode]>;
 
@@ -3374,32 +3374,32 @@ def : Pat<(sext_inreg GR16:$src, i8),
 def : Pat<(i16 (trunc GR32:$src)),
           (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
 def : Pat<(i8 (trunc GR32:$src)),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc GR16:$src)),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                           x86_subreg_8bit)>,
       Requires<[In32BitMode]>;
 
 // h-register tricks
 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
-          (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                           x86_subreg_8bit_hi)>,
       Requires<[In32BitMode]>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32rr8
-              (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR16:$src, GR16_),
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In32BitMode]>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
-          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_SUBCLASS GR32:$src, GR32_),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
                                       x86_subreg_8bit_hi))>,
       Requires<[In32BitMode]>;
 
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 912617bc01d..7b0a335b26b 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -34,7 +34,7 @@ void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
         R->getName() == "INSERT_SUBREG" ||
         R->getName() == "IMPLICIT_DEF" ||
         R->getName() == "SUBREG_TO_REG" ||
-        R->getName() == "COPY_TO_SUBCLASS") continue;
+        R->getName() == "COPY_TO_REGCLASS") continue;
 
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -111,7 +111,7 @@ void CodeEmitterGen::run(std::ostream &o) {
         R->getName() == "INSERT_SUBREG" ||
         R->getName() == "IMPLICIT_DEF" ||
         R->getName() == "SUBREG_TO_REG" ||
-        R->getName() == "COPY_TO_SUBCLASS") {
+        R->getName() == "COPY_TO_REGCLASS") {
       o << "    0U,\n";
       continue;
     }
@@ -149,7 +149,7 @@ void CodeEmitterGen::run(std::ostream &o) {
         InstName == "INSERT_SUBREG" ||
         InstName == "IMPLICIT_DEF" ||
         InstName == "SUBREG_TO_REG" ||
-        InstName == "COPY_TO_SUBCLASS") continue;
+        InstName == "COPY_TO_REGCLASS") continue;
 
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index eb0b0990488..804d1df128a 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -884,7 +884,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
       MadeChange = getChild(i)->ApplyTypeConstraints(TP, NotRegisters);
     MadeChange |= UpdateNodeType(MVT::isVoid, TP);
     return MadeChange;
-  } else if (getOperator()->getName() == "COPY_TO_SUBCLASS") {
+  } else if (getOperator()->getName() == "COPY_TO_REGCLASS") {
     bool MadeChange = false;
     MadeChange |= getChild(0)->ApplyTypeConstraints(TP, NotRegisters);
     MadeChange |= getChild(1)->ApplyTypeConstraints(TP, NotRegisters);
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index c5d4c494c03..0c9da806cc9 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -345,10 +345,10 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
     throw "Could not find 'SUBREG_TO_REG' instruction!";
   const CodeGenInstruction *SUBREG_TO_REG = &I->second;
 
-  I = getInstructions().find("COPY_TO_SUBCLASS");
+  I = getInstructions().find("COPY_TO_REGCLASS");
   if (I == Instructions.end())
-    throw "Could not find 'COPY_TO_SUBCLASS' instruction!";
-  const CodeGenInstruction *COPY_TO_SUBCLASS = &I->second;
+    throw "Could not find 'COPY_TO_REGCLASS' instruction!";
+  const CodeGenInstruction *COPY_TO_REGCLASS = &I->second;
 
   // Print out the rest of the instructions now.
   NumberedInstructions.push_back(PHI);
@@ -361,7 +361,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
   NumberedInstructions.push_back(INSERT_SUBREG);
   NumberedInstructions.push_back(IMPLICIT_DEF);
   NumberedInstructions.push_back(SUBREG_TO_REG);
-  NumberedInstructions.push_back(COPY_TO_SUBCLASS);
+  NumberedInstructions.push_back(COPY_TO_REGCLASS);
   for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
     if (&II->second != PHI &&
         &II->second != INLINEASM &&
@@ -373,7 +373,7 @@ getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
         &II->second != INSERT_SUBREG &&
         &II->second != IMPLICIT_DEF &&
         &II->second != SUBREG_TO_REG &&
-        &II->second != COPY_TO_SUBCLASS)
+        &II->second != COPY_TO_REGCLASS)
       NumberedInstructions.push_back(&II->second);
 }
 
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 1a32828e7dd..61dbe64af8f 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -341,7 +341,7 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
         R->getName() != "INSERT_SUBREG" &&
         R->getName() != "IMPLICIT_DEF" &&
         R->getName() != "SUBREG_TO_REG" &&
-        R->getName() != "COPY_TO_SUBCLASS")
+        R->getName() != "COPY_TO_REGCLASS")
       throw R->getName() + " doesn't have a field named '" + 
             Val->getValue() + "'!";
     return;