diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-03-02 18:19:40 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-02 18:19:40 +0000 |
| commit | 6b1419b547d2d5ee523250efd60ccc3d6ce8279c (patch) | |
| tree | 9d78d5d9404601ce2ec86c64172d0d2411b2f762 | |
| parent | 18799f4c07fdef192ab8b42b9e954baad97a23f5 (diff) | |
| download | bcm5719-llvm-6b1419b547d2d5ee523250efd60ccc3d6ce8279c.tar.gz bcm5719-llvm-6b1419b547d2d5ee523250efd60ccc3d6ce8279c.zip | |
[X86] Reject xmm16-31 in inline asm constraints when AVX512 is disabled
Fixes PR36532
Differential Revision: https://reviews.llvm.org/D43960
llvm-svn: 326596
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/asm-reject-xmm16.ll | 8 |
2 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 56c6bd9d268..15115115b92 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39160,6 +39160,15 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return Res; } + // Make sure it isn't a register that requires AVX512. + if (!Subtarget.hasAVX512() && isFRClass(*Res.second) && + TRI->getEncodingValue(Res.first) & 0x10) { + // Register requires EVEX prefix. + Res.first = 0; + Res.second = nullptr; + return Res; + } + // Otherwise, check to see if this is a register class of the wrong value // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to // turn into {ax},{dx}. diff --git a/llvm/test/CodeGen/X86/asm-reject-xmm16.ll b/llvm/test/CodeGen/X86/asm-reject-xmm16.ll new file mode 100644 index 00000000000..eee0064c964 --- /dev/null +++ b/llvm/test/CodeGen/X86/asm-reject-xmm16.ll @@ -0,0 +1,8 @@ +; RUN: not llc -o /dev/null %s 2>&1 | FileCheck %s +target triple = "x86_64--" + +; CHECK: error: couldn't allocate output register for constraint '{xmm16}' +define i64 @blup() { + %v = tail call i64 asm "", "={xmm16},0"(i64 0) + ret i64 %v +} |

