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authorCraig Topper <craig.topper@intel.com>2018-08-29 04:45:32 +0000
committerCraig Topper <craig.topper@intel.com>2018-08-29 04:45:32 +0000
commit6b03f267b0aac8cbebb6244a38779ae503a2e5f4 (patch)
tree42175b4d2f678c85b0d256df133c60d95369eb0d
parentb2fef1a0b0c2193bd9aba957b8050098728c5405 (diff)
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[SelectionDAG] Add some comments to ISDOpcodes.h about the operands of MLOAD, MSTORE, MGATHER, MSCATTER. NFC
llvm-svn: 340898
-rw-r--r--llvm/include/llvm/CodeGen/ISDOpcodes.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 80bd796d537..842f27f19e1 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -786,11 +786,20 @@ namespace ISD {
// Masked load and store - consecutive vector load and store operations
// with additional mask operand that prevents memory accesses to the
// masked-off lanes.
+ //
+ // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
+ // OutChain = MSTORE(Value, BasePtr, Mask)
MLOAD, MSTORE,
// Masked gather and scatter - load and store operations for a vector of
// random addresses with additional mask operand that prevents memory
// accesses to the masked-off lanes.
+ //
+ // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
+ // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
+ //
+ // The Index operand can have more vector elements than the other operands
+ // due to type legalization. The extra elements are ignored.
MGATHER, MSCATTER,
/// This corresponds to the llvm.lifetime.* intrinsics. The first operand
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