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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-07-19 10:49:03 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2016-07-19 10:49:03 +0000 |
| commit | 6a73883c48fbeb43009f3373bbf82e1c70ff96eb (patch) | |
| tree | afeb74dee72aed1a8c87b7f91c4123d6bfd4d086 | |
| parent | 2cb55d7dfdfbc92ce77705f5c31e629bb09b45bb (diff) | |
| download | bcm5719-llvm-6a73883c48fbeb43009f3373bbf82e1c70ff96eb.tar.gz bcm5719-llvm-6a73883c48fbeb43009f3373bbf82e1c70ff96eb.zip | |
[mips] Correct label prefixes for N32 and N64.
Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).
This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D22412
llvm-svn: 275967
35 files changed, 400 insertions, 280 deletions
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 909c7dd00ac..30e75847cb1 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -7105,9 +7105,9 @@ class MipsTargetInfo : public TargetInfo { if (ABI == "o32") Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; else if (ABI == "n32") - Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; + Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; else if (ABI == "n64") - Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; + Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; else llvm_unreachable("Invalid ABI"); diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c index 49406a30e5d..c12ad2c1c97 100644 --- a/clang/test/CodeGen/target-data.c +++ b/clang/test/CodeGen/target-data.c @@ -40,19 +40,19 @@ // RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=MIPS-64EL -// MIPS-64EL: target datalayout = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128" +// MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" // RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \ // RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32 -// MIPS-64EL-N32: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" +// MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=MIPS-64EB -// MIPS-64EB: target datalayout = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128" +// MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128" // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \ // RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32 -// MIPS-64EB-N32: target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" +// MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128" // RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=PS3 diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index 1622b221266..1ce8f07092b 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -28,12 +28,19 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) { PointerSize = CalleeSaveStackSlotSize = 8; } + // FIXME: This condition isn't quite right but it's the best we can do until + // this object can identify the ABI. It will misbehave when using O32 + // on a mips64*-* triple. + if ((TheTriple.getArch() == Triple::mipsel) || + (TheTriple.getArch() == Triple::mips)) { + PrivateGlobalPrefix = "$"; + PrivateLabelPrefix = "$"; + } + AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Data32bitsDirective = "\t.4byte\t"; Data64bitsDirective = "\t.8byte\t"; - PrivateGlobalPrefix = "$"; - PrivateLabelPrefix = "$"; CommentString = "#"; ZeroDirective = "\t.space\t"; GPRel32Directive = "\t.gpword\t"; diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index c248c3a50ac..80641ed9bd3 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -57,7 +57,10 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, else Ret += "E"; - Ret += "-m:m"; + if (ABI.IsO32()) + Ret += "-m:m"; + else + Ret += "-m:e"; // Pointers are 32 bit on some ABIs. if (!ABI.IsN64()) diff --git a/llvm/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/llvm/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index f736ddd0def..c0229c626a0 100644 --- a/llvm/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/llvm/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -11,13 +11,13 @@ entry: ; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) ; STATIC-O32: lui $[[R0:[0-9]+]], %hi($CPI0_0) ; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) -; PIC-N32: lw $[[R0:[0-9]+]], %got_page($CPI0_0) -; PIC-N32: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) -; STATIC-N32: lui $[[R0:[0-9]+]], %hi($CPI0_0) -; STATIC-N32: lwc1 $f0, %lo($CPI0_0)($[[R0]]) -; PIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) -; PIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) -; STATIC-N64: ld $[[R0:[0-9]+]], %got_page($CPI0_0) -; STATIC-N64: lwc1 $f0, %got_ofst($CPI0_0)($[[R0]]) +; PIC-N32: lw $[[R0:[0-9]+]], %got_page(.LCPI0_0) +; PIC-N32: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]]) +; STATIC-N32: lui $[[R0:[0-9]+]], %hi(.LCPI0_0) +; STATIC-N32: lwc1 $f0, %lo(.LCPI0_0)($[[R0]]) +; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0) +; PIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]]) +; STATIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0) +; STATIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]]) ret float 0x400B333340000000 } diff --git a/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll b/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll index 7d66d1a1a20..5f0a0a5a492 100644 --- a/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/llvm/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -27,9 +27,9 @@ entry: ; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; PIC-O32: jr $[[R5]] ; N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3 -; N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0) +; N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0) ; N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]] -; N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]]) +; N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]]) ; N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]] ; N64: jr $[[R5]] switch i32 %0, label %bb4 [ @@ -68,7 +68,7 @@ bb5: ; preds = %entry ; PIC-O32: .gpword ; PIC-O32: .gpword ; N64: .p2align 3 -; N64: $JTI0_0: +; N64: .LJTI0_0: ; N64: .gpdword ; N64: .gpdword ; N64: .gpdword diff --git a/llvm/test/CodeGen/Mips/analyzebranch.ll b/llvm/test/CodeGen/Mips/analyzebranch.ll index 377fe9327e0..62150875e75 100644 --- a/llvm/test/CodeGen/Mips/analyzebranch.ll +++ b/llvm/test/CodeGen/Mips/analyzebranch.ll @@ -10,7 +10,7 @@ define double @foo(double %a, double %b) nounwind readnone { entry: ; ALL-LABEL: foo: -; FCC: bc1f $BB +; FCC: bc1f {{\$|\.L}}BB ; FCC: nop ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]] @@ -19,7 +19,7 @@ entry: ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnezc $[[GPRCC]], $BB +; GPR: bnezc $[[GPRCC]], {{\$|\.L}}BB %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -43,7 +43,7 @@ define void @f1(float %f) nounwind { entry: ; ALL-LABEL: f1: -; FCC: bc1f $BB +; FCC: bc1f {{\$|\.L}}BB ; FCC: nop ; GPR: mtc1 $zero, $[[Z:f[0-9]]] diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll index 8f4ccb19958..dfba8ba1933 100644 --- a/llvm/test/CodeGen/Mips/atomic.ll +++ b/llvm/test/CodeGen/Mips/atomic.ll @@ -34,17 +34,17 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( -; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; O0: ld $[[R1:[0-9]+]] ; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]]) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R3:[0-9]+]], 0($[[R0]]) ; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4 ; ALL: sc $[[R4]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R4]], $[[BB0]] -; MICROMIPS: beqzc $[[R4]], $[[BB0]] -; MIPSR6: beqzc $[[R4]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R4]], [[BB0]] +; MICROMIPS: beqzc $[[R4]], [[BB0]] +; MIPSR6: beqzc $[[R4]], [[BB0]] } define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { @@ -59,14 +59,14 @@ entry: -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 ; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; ALL: sc $[[R2]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] -; MIPSR6: beqzc $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] +; MICROMIPS: beqzc $[[R2]], [[BB0]] +; MIPSR6: beqzc $[[R2]], [[BB0]] } define i32 @AtomicSwap32(i32 signext %newval) nounwind { @@ -82,12 +82,12 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll ${{[0-9]+}}, 0($[[R0]]) ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] -; MIPSR6: beqzc $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] +; MICROMIPS: beqzc $[[R2]], [[BB0]] +; MIPSR6: beqzc $[[R2]], [[BB0]] } define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { @@ -104,16 +104,16 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $2, 0($[[R0]]) -; NOT-MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] -; MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] -; MIPSR6: bnec $2, $4, $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MICROMIPS: bne $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MIPSR6: bnec $2, $4, [[BB1:(\$|\.L)[A-Z_0-9]+]] ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] -; MIPSR6: beqzc $[[R2]], $[[BB0]] -; ALL: $[[BB1]]: +; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] +; MICROMIPS: beqzc $[[R2]], [[BB0]] +; MIPSR6: beqzc $[[R2]], [[BB0]] +; ALL: [[BB1]]: } @@ -141,20 +141,20 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; O0: ld $[[R10:[0-9]+]] ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] -; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; MIPSR6: beqzc $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] +; MICROMIPS: beqzc $[[R16]], [[BB0]] +; MIPSR6: beqzc $[[R16]], [[BB0]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] @@ -186,20 +186,20 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; O0: ld $[[R10:[0-9]+]] ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] -; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; MIPSR6: beqzc $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] +; MICROMIPS: beqzc $[[R16]], [[BB0]] +; MIPSR6: beqzc $[[R16]], [[BB0]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] @@ -231,11 +231,11 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; O0: ld $[[R10:[0-9]+]] ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]] @@ -243,9 +243,9 @@ entry: ; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]] ; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]] ; ALL: sc $[[R17]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R17]], $[[BB0]] -; MICROMIPS: beqzc $[[R17]], $[[BB0]] -; MIPSR6: beqzc $[[R17]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R17]], [[BB0]] +; MICROMIPS: beqzc $[[R17]], [[BB0]] +; MIPSR6: beqzc $[[R17]], [[BB0]] ; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]] ; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]] @@ -277,15 +277,15 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] -; MIPSR6: beqzc $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] +; MICROMIPS: beqzc $[[R14]], [[BB0]] +; MIPSR6: beqzc $[[R14]], [[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -322,21 +322,21 @@ entry: ; ALL: andi $[[R11:[0-9]+]], $5, 255 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] -; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] -; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] -; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; MIPSR6: beqzc $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] +; MICROMIPS: beqzc $[[R16]], [[BB0]] +; MIPSR6: beqzc $[[R16]], [[BB0]] -; ALL: $[[BB1]]: +; ALL: [[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 @@ -366,21 +366,21 @@ entry: ; ALL: andi $[[R11:[0-9]+]], $6, 255 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] -; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] -; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], [[BB1:(\$|\.L)[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] -; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; MIPSR6: beqzc $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] +; MICROMIPS: beqzc $[[R16]], [[BB0]] +; MIPSR6: beqzc $[[R16]], [[BB0]] -; ALL: $[[BB1]]: +; ALL: [[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 @@ -423,20 +423,20 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; O0: ld $[[R10:[0-9]+]] ; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] -; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; MIPSR6: beqzc $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] +; MICROMIPS: beqzc $[[R16]], [[BB0]] +; MIPSR6: beqzc $[[R16]], [[BB0]] ; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] ; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] @@ -465,15 +465,15 @@ define {i16, i1} @foo(i16* %addr, i16 %l, i16 %r, i16 %new) { ; ALL: sync ; ALL: andi $[[R3:[0-9]+]], $[[R2]], 65535 -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R4:[0-9]+]], 0($[[R5:[0-9]+]]) ; ALL: and $[[R6:[0-9]+]], $[[R4]], $ ; ALL: and $[[R7:[0-9]+]], $[[R4]], $ ; ALL: or $[[R8:[0-9]+]], $[[R7]], $ ; ALL: sc $[[R8]], 0($[[R5]]) -; NOT-MICROMIPS: beqz $[[R8]], $[[BB0]] -; MICROMIPS: beqzc $[[R8]], $[[BB0]] -; MIPSR6: beqzc $[[R8]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R8]], [[BB0]] +; MICROMIPS: beqzc $[[R8]], [[BB0]] +; MIPSR6: beqzc $[[R8]], [[BB0]] ; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $ @@ -538,11 +538,11 @@ entry: ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024 -; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: [[BB0:(\$|\.L)[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]]) ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: sc $[[R2]], 0($[[PTR]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] -; MIPSR6: beqzc $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] +; MICROMIPS: beqzc $[[R2]], [[BB0]] +; MIPSR6: beqzc $[[R2]], [[BB0]] } diff --git a/llvm/test/CodeGen/Mips/blez_bgez.ll b/llvm/test/CodeGen/Mips/blez_bgez.ll index dcda047f8d0..84c8af45db8 100644 --- a/llvm/test/CodeGen/Mips/blez_bgez.ll +++ b/llvm/test/CodeGen/Mips/blez_bgez.ll @@ -2,7 +2,7 @@ ; RUN: llc -march=mips64el < %s | FileCheck %s ; CHECK-LABEL: test_blez: -; CHECK: blez ${{[0-9]+}}, $BB +; CHECK: blez ${{[0-9]+}}, {{\$|\.L}}BB define void @test_blez(i32 %a) { entry: @@ -20,7 +20,7 @@ if.end: declare void @foo1() ; CHECK-LABEL: test_bgez: -; CHECK: bgez ${{[0-9]+}}, $BB +; CHECK: bgez ${{[0-9]+}}, {{\$|\.L}}BB define void @test_bgez(i32 %a) { entry: diff --git a/llvm/test/CodeGen/Mips/blockaddr.ll b/llvm/test/CodeGen/Mips/blockaddr.ll index f74363702af..9bc9a305a20 100644 --- a/llvm/test/CodeGen/Mips/blockaddr.ll +++ b/llvm/test/CodeGen/Mips/blockaddr.ll @@ -22,22 +22,22 @@ entry: ; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) ; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) ; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) -; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) -; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) -; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) -; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) -; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) -; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) -; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) -; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) -; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) -; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) -; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]]) -; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]]) +; PIC-N32: lw $[[R0:[0-9]+]], %got_page(.Ltmp[[T0:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]]) +; PIC-N32: lw $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]]) +; STATIC-N32: lui $[[R2:[0-9]+]], %hi(.Ltmp[[T2:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo(.Ltmp[[T2]]) +; STATIC-N32: lui $[[R3:[0-9]+]], %hi(.Ltmp[[T3:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo(.Ltmp[[T3]]) +; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.Ltmp[[T0:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst(.Ltmp[[T0]]) +; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.Ltmp[[T1:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst(.Ltmp[[T1]]) +; STATIC-N64: ld $[[R2:[0-9]+]], %got_page(.Ltmp[[T2:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst(.Ltmp[[T2]]) +; STATIC-N64: ld $[[R3:[0-9]+]], %got_page(.Ltmp[[T3:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst(.Ltmp[[T3]]) ; STATIC-MIPS16-1: .ent f ; STATIC-MIPS16-2: .ent f ; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]]) diff --git a/llvm/test/CodeGen/Mips/ehframe-indirect.ll b/llvm/test/CodeGen/Mips/ehframe-indirect.ll index d6d47678590..9352294991a 100644 --- a/llvm/test/CodeGen/Mips/ehframe-indirect.ll +++ b/llvm/test/CodeGen/Mips/ehframe-indirect.ll @@ -33,9 +33,15 @@ declare void @foo() ; ALL: GCC_except_table{{[0-9]+}}: ; ALL: .byte 155 # @TType Encoding = indirect pcrel sdata4 -; ALL: $[[PC_LABEL:tmp[0-9]+]]: -; ALL: .4byte ($_ZTISt9exception.DW.stub)-($[[PC_LABEL]]) -; ALL: $_ZTISt9exception.DW.stub: +; O32: [[PC_LABEL:\$tmp[0-9]+]]: +; N32: [[PC_LABEL:\.Ltmp[0-9]+]]: +; N64: [[PC_LABEL:\.Ltmp[0-9]+]]: +; O32: .4byte ($_ZTISt9exception.DW.stub)-([[PC_LABEL]]) +; N32: .4byte .L_ZTISt9exception.DW.stub-[[PC_LABEL]] +; N64: .4byte .L_ZTISt9exception.DW.stub-[[PC_LABEL]] +; O32: $_ZTISt9exception.DW.stub: +; N32: .L_ZTISt9exception.DW.stub: +; N64: .L_ZTISt9exception.DW.stub: ; O32: .4byte _ZTISt9exception ; N32: .4byte _ZTISt9exception ; N64: .8byte _ZTISt9exception diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll index 142ee1144bb..bd04ed0211f 100644 --- a/llvm/test/CodeGen/Mips/fcmp.ll +++ b/llvm/test/CodeGen/Mips/fcmp.ll @@ -1076,12 +1076,12 @@ entry: ; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( +; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)( ; 64-C-DAG: c.ole.s $[[T0]], $[[T1]] ; 64-C-DAG: bc1t ; 64-CMP-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( +; 64-CMP-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI32_0)( ; 64-CMP-DAG: cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. @@ -1106,8 +1106,8 @@ entry: ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32))) ; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]]) -; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]]) +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI32_0)($[[T2]]) +; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI32_0)($[[T4]]) ; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]] ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 @@ -1145,12 +1145,12 @@ entry: ; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( +; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)( ; 64-C-DAG: c.ole.d $[[T0]], $[[T1]] ; 64-C-DAG: bc1t ; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( +; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst(.LCPI33_0)( ; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]] ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. @@ -1175,8 +1175,8 @@ entry: ; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 ; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64))) ; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]]) -; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]]) +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page(.LCPI33_0)($[[T2]]) +; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst(.LCPI33_0)($[[T4]]) ; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]] ; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] ; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index bf1b045dbf2..7fb508f606b 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -10,8 +10,9 @@ entry: ; ALL-LABEL: func0: ; 32-FCC: c.eq.s $f12, $f14 +; 32-FCC: bc1f $BB0_2 ; 64-FCC: c.eq.s $f12, $f13 -; FCC: bc1f $BB0_2 +; 64-FCC: bc1f .LBB0_2 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13 @@ -19,7 +20,7 @@ entry: ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: bnez $[[GPRCC]], $BB0_2 -; 64-GPR: bnezc $[[GPRCC]], $BB0_2 +; 64-GPR: bnezc $[[GPRCC]], .LBB0_2 %cmp = fcmp oeq float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -45,15 +46,16 @@ entry: ; ALL-LABEL: func1: ; 32-FCC: c.olt.s $f12, $f14 +; 32-FCC: bc1f $BB1_2 ; 64-FCC: c.olt.s $f12, $f13 -; FCC: bc1f $BB1_2 +; 64-FCC: bc1f .LBB1_2 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: bnez $[[GPRCC]], $BB1_2 -; 64-GPR: bnezc $[[GPRCC]], $BB1_2 +; 64-GPR: bnezc $[[GPRCC]], .LBB1_2 %cmp = fcmp olt float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -75,15 +77,16 @@ entry: ; ALL-LABEL: func2: ; 32-FCC: c.ole.s $f12, $f14 +; 32-FCC: bc1t $BB2_2 ; 64-FCC: c.ole.s $f12, $f13 -; FCC: bc1t $BB2_2 +; 64-FCC: bc1t .LBB2_2 ; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: beqz $[[GPRCC]], $BB2_2 -; 64-GPR: beqzc $[[GPRCC]], $BB2_2 +; 64-GPR: beqzc $[[GPRCC]], .LBB2_2 %cmp = fcmp ugt float %f2, %f3 br i1 %cmp, label %if.else, label %if.then @@ -105,8 +108,9 @@ entry: ; ALL-LABEL: func3: ; 32-FCC: c.eq.d $f12, $f14 +; 32-FCC: bc1f $BB3_2 ; 64-FCC: c.eq.d $f12, $f13 -; FCC: bc1f $BB3_2 +; 64-FCC: bc1f .LBB3_2 ; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13 @@ -114,7 +118,7 @@ entry: ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: bnez $[[GPRCC]], $BB3_2 -; 64-GPR: bnezc $[[GPRCC]], $BB3_2 +; 64-GPR: bnezc $[[GPRCC]], .LBB3_2 %cmp = fcmp oeq double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -136,15 +140,16 @@ entry: ; ALL-LABEL: func4: ; 32-FCC: c.olt.d $f12, $f14 +; 32-FCC: bc1f $BB4_2 ; 64-FCC: c.olt.d $f12, $f13 -; FCC: bc1f $BB4_2 +; 64-FCC: bc1f .LBB4_2 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: bnez $[[GPRCC]], $BB4_2 -; 64-GPR: bnezc $[[GPRCC]], $BB4_2 +; 64-GPR: bnezc $[[GPRCC]], .LBB4_2 %cmp = fcmp olt double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -166,15 +171,16 @@ entry: ; ALL-LABEL: func5: ; 32-FCC: c.ole.d $f12, $f14 +; 32-FCC: bc1t $BB5_2 ; 64-FCC: c.ole.d $f12, $f13 -; FCC: bc1t $BB5_2 +; 64-FCC: bc1t .LBB5_2 ; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] ; 32-GPR: beqz $[[GPRCC]], $BB5_2 -; 64-GPR: beqzc $[[GPRCC]], $BB5_2 +; 64-GPR: beqzc $[[GPRCC]], .LBB5_2 %cmp = fcmp ugt double %f2, %f3 br i1 %cmp, label %if.else, label %if.then diff --git a/llvm/test/CodeGen/Mips/jumptable_labels.ll b/llvm/test/CodeGen/Mips/jumptable_labels.ll new file mode 100644 index 00000000000..8c7edc10689 --- /dev/null +++ b/llvm/test/CodeGen/Mips/jumptable_labels.ll @@ -0,0 +1,75 @@ +; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 +; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefix=N64 + +; We only use the '$' prefix on O32. The others use the ELF convention. +; O32: $JTI0_0 +; N32: .LJTI0_0 +; N64: .LJTI0_0 + +; Check basic block labels while we're at it. +; O32: $BB0_2: +; N32: .LBB0_2: +; N64: .LBB0_2: + +@.str = private unnamed_addr constant [2 x i8] c"A\00", align 1 +@.str.1 = private unnamed_addr constant [2 x i8] c"B\00", align 1 +@.str.2 = private unnamed_addr constant [2 x i8] c"C\00", align 1 +@.str.3 = private unnamed_addr constant [2 x i8] c"D\00", align 1 +@.str.4 = private unnamed_addr constant [2 x i8] c"E\00", align 1 +@.str.5 = private unnamed_addr constant [2 x i8] c"F\00", align 1 +@.str.6 = private unnamed_addr constant [2 x i8] c"G\00", align 1 +@.str.7 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 + +define i8* @_Z3fooi(i32 signext %Letter) { +entry: + %retval = alloca i8*, align 8 + %Letter.addr = alloca i32, align 4 + store i32 %Letter, i32* %Letter.addr, align 4 + %0 = load i32, i32* %Letter.addr, align 4 + switch i32 %0, label %sw.epilog [ + i32 0, label %sw.bb + i32 1, label %sw.bb1 + i32 2, label %sw.bb2 + i32 3, label %sw.bb3 + i32 4, label %sw.bb4 + i32 5, label %sw.bb5 + i32 6, label %sw.bb6 + ] + +sw.bb: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb1: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.1, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb2: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.2, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb3: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.3, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb4: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.4, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb5: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.5, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.bb6: + store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.6, i32 0, i32 0), i8** %retval, align 8 + br label %return + +sw.epilog: + store i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str.7, i32 0, i32 0), i8** %retval, align 8 + br label %return + +return: + %1 = load i8*, i8** %retval, align 8 + ret i8* %1 +} diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll index af9b81f9203..cfb9855e643 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -167,18 +167,18 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]] ; M3: move $3, $[[T1]] ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $3, $[[T7]], $[[T4]] - ; M3: $[[BB0]]: - ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: [[BB0]]: + ; M3: beqz $[[T3]], [[BB1:.LBB[0-9_]+]] ; M3: nop ; M3: dsra $2, $4, 63 - ; M3: $[[BB1]]: + ; M3: [[BB1]]: ; M3: jr $ra ; M3: nop diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll index d982b570d7c..8fed32aee9b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -18,13 +18,13 @@ define i32 @br(i8 *%addr) { ; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC -; ALL: $BB0_1: # %L1 +; ALL: {{\$|\.L}}BB0_1: # %L1 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; ALL: addiu $2, $zero, 0 -; ALL: $BB0_2: # %L2 +; ALL: {{\$|\.L}}BB0_2: # %L2 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index 10748b9c803..63fb075a4ad 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -158,18 +158,18 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] ; M3: move $3, $[[T1]] ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $3, $[[T7]], $[[T4]] - ; M3: $[[BB0]]: - ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: [[BB0]]: + ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]] ; M3: daddiu $2, $zero, 0 ; M3: move $2, $[[T1]] - ; M3: $[[BB1]]: + ; M3: [[BB1]]: ; M3: jr $ra ; M3: nop diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll index 1ca5b4e054b..42f02c4cbab 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -58,10 +58,10 @@ entry: ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:.LBB[0-9_]+]] ; M3: nop ; M3: mov.d $f13, $f14 - ; M3: $[[BB0]]: + ; M3: [[BB0]]: ; M3: jr $ra ; M3: mov.d $f0, $f13 @@ -106,10 +106,10 @@ entry: ; SEL-32: sel.d $f0, $f14, $f12 ; M3: andi $[[T0:[0-9]+]], $6, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M3: nop ; M3: mov.d $f12, $f13 - ; M3: $[[BB0]]: + ; M3: [[BB0]]: ; M3: jr $ra ; M3: mov.d $f0, $f12 @@ -135,11 +135,12 @@ entry: ; M2: c.olt.d $f12, $f14 ; M3: c.olt.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 @@ -172,11 +173,12 @@ entry: ; M2: c.ole.d $f12, $f14 ; M3: c.ole.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 @@ -209,11 +211,12 @@ entry: ; M2: c.ule.d $f12, $f14 ; M3: c.ule.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 @@ -246,11 +249,12 @@ entry: ; M2: c.ult.d $f12, $f14 ; M3: c.ult.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 @@ -283,11 +287,12 @@ entry: ; M2: c.eq.d $f12, $f14 ; M3: c.eq.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 @@ -320,11 +325,12 @@ entry: ; M2: c.ueq.d $f12, $f14 ; M3: c.ueq.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.d $f12, $f14 ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.d $f0, $f12 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll index 6a0334da483..e632897e76c 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -34,12 +34,13 @@ entry: ; ALL-LABEL: tst_select_i1_float: ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: jr $ra ; M2: mtc1 $6, $f0 ; M3: mov.s $f13, $f14 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2: mtc1 $5, $f0 ; M3: mov.s $f0, $f13 @@ -76,11 +77,12 @@ entry: ; ALL-LABEL: tst_select_i1_float_reordered: ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -112,11 +114,12 @@ entry: ; M2: c.olt.s $f12, $f14 ; M3: c.olt.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -149,11 +152,12 @@ entry: ; M2: c.ole.s $f12, $f14 ; M3: c.ole.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -186,11 +190,12 @@ entry: ; M2: c.ule.s $f12, $f14 ; M3: c.ule.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -223,11 +228,12 @@ entry: ; M2: c.ult.s $f12, $f14 ; M3: c.ult.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -260,11 +266,12 @@ entry: ; M2: c.eq.s $f12, $f14 ; M3: c.eq.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2: bc1t [[BB0:\$BB[0-9_]+]] + ; M3: bc1t [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 @@ -297,11 +304,12 @@ entry: ; M2: c.ueq.s $f12, $f14 ; M3: c.ueq.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2: bc1f [[BB0:\$BB[0-9_]+]] + ; M3: bc1f [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2: mov.s $f12, $f14 ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: mov.s $f0, $f12 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll index e8f78ffdcb6..5bee3f1dbd5 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -35,10 +35,11 @@ entry: ; ALL-LABEL: tst_select_i1_i1: ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: move $2, $5 @@ -70,10 +71,11 @@ entry: ; ALL-LABEL: tst_select_i1_i8: ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: move $2, $5 @@ -105,10 +107,11 @@ entry: ; ALL-LABEL: tst_select_i1_i32: ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M2-M3: nop ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: + ; M2-M3: [[BB0]]: ; M2-M3: jr $ra ; M2-M3: move $2, $5 @@ -170,10 +173,10 @@ entry: ; SEL-32: or $3, $[[T4]], $[[T6]] ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] ; M3: nop ; M3: move $5, $6 - ; M3: $[[BB0]]: + ; M3: [[BB0]]: ; M3: jr $ra ; M3: move $2, $5 @@ -214,19 +217,19 @@ define i8* @tst_select_word_cst(i8* %a, i8* %b) { ; M2: addiu $[[T0:[0-9]+]], $zero, -1 ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]] ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]] - ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]] ; M2: addiu $2, $zero, 0 ; M2: move $2, $4 - ; M2: $[[BB0]]: + ; M2: [[BB0]]: ; M2: jr $ra ; M3: daddiu $[[T0:[0-9]+]], $zero, -1 ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]] ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]] - ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T2]], [[BB0:\.LBB[0-9_]+]] ; M3: daddiu $2, $zero, 0 ; M3: move $2, $4 - ; M3: $[[BB0]]: + ; M3: [[BB0]]: ; M3: jr $ra ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll index fa43840a8b7..74b6155032a 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll @@ -174,18 +174,18 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]] ; M3: move $2, $[[T1]] ; M3: dsllv $[[T4:[0-9]+]], $4, $7 ; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $2, $[[T4]], $[[T7]] - ; M3: $[[BB0]]: - ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: [[BB0]]: + ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]] ; M3: daddiu $3, $zero, 0 ; M3: move $3, $[[T1]] - ; M3: $[[BB1]]: + ; M3: [[BB1]]: ; M3: jr $ra ; M3: nop diff --git a/llvm/test/CodeGen/Mips/longbranch.ll b/llvm/test/CodeGen/Mips/longbranch.ll index 06eda11e788..59e284165d4 100644 --- a/llvm/test/CodeGen/Mips/longbranch.ll +++ b/llvm/test/CodeGen/Mips/longbranch.ll @@ -84,28 +84,28 @@ end: ; Check the MIPS64 version. ; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) -; N64: bnez $4, $[[BB0:BB[0-9_]+]] +; N64: bnez $4, [[BB0:\.LBB[0-9_]+]] ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 ; Check for long branch expansion: ; N64: daddiu $sp, $sp, -16 ; N64-NEXT: sd $ra, 0($sp) -; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) +; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]]) ; N64-NEXT: dsll $1, $1, 16 -; N64-NEXT: bal $[[BB1]] -; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) -; N64-NEXT: $[[BB1]]: +; N64-NEXT: bal [[BB1]] +; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]]) +; N64-NEXT: [[BB1]]: ; N64-NEXT: daddu $1, $ra, $1 ; N64-NEXT: ld $ra, 0($sp) ; N64-NEXT: jr $1 ; N64-NEXT: daddiu $sp, $sp, 16 -; N64: $[[BB0]]: +; N64: [[BB0]]: ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: addiu $[[R3:[0-9]+]], $zero, 1 ; N64: sw $[[R3]], 0($[[R2]]) -; N64: $[[BB2]]: +; N64: [[BB2]]: ; N64: jr $ra ; N64: nop diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll index 5d253d7af25..d7a05800a27 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll @@ -36,14 +36,14 @@ define void @const_v16i8() nounwind { store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8 @@ -59,8 +59,8 @@ define void @const_v16i8() nounwind { store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.b [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -77,8 +77,8 @@ define void @const_v8i16() nounwind { store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16 @@ -93,8 +93,8 @@ define void @const_v8i16() nounwind { store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.h [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -111,8 +111,8 @@ define void @const_v4i32() nounwind { store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32 @@ -123,14 +123,14 @@ define void @const_v4i32() nounwind { store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -156,15 +156,15 @@ define void @const_v2i64() nounwind { store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll index d714b3eec1f..15468781f30 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -23,8 +23,8 @@ define void @const_v4f32() nounwind { store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32 @@ -34,14 +34,14 @@ define void @const_v4f32() nounwind { store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void @@ -55,38 +55,38 @@ define void @const_v2f64() nounwind { store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64 ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ - ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($ + ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L + ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst(.L ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) ret void diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll index b441274cec6..7e2a81019ac 100644 --- a/llvm/test/CodeGen/Mips/octeon.ll +++ b/llvm/test/CodeGen/Mips/octeon.ll @@ -91,9 +91,9 @@ entry: define i64 @bbit0(i64 %a) nounwind { entry: ; ALL-LABEL: bbit0: -; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]] +; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 -; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]] +; MIPS64: bnez $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 8 %res = icmp eq i64 %bit, 0 br i1 %res, label %endif, label %if @@ -107,11 +107,11 @@ endif: define i64 @bbit032(i64 %a) nounwind { entry: ; ALL-LABEL: bbit032: -; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]] +; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] -; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]] +; MIPS64: bnez $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 34359738368 %res = icmp eq i64 %bit, 0 br i1 %res, label %endif, label %if @@ -125,9 +125,9 @@ endif: define i64 @bbit1(i64 %a) nounwind { entry: ; ALL-LABEL: bbit1: -; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]] +; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] ; MIPS64: andi $[[T0:[0-9]+]], $4, 8 -; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]] +; MIPS64: beqz $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 8 %res = icmp ne i64 %bit, 0 br i1 %res, label %endif, label %if @@ -141,11 +141,11 @@ endif: define i64 @bbit132(i64 %a) nounwind { entry: ; ALL-LABEL: bbit132: -; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]] +; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]] ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1 ; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35 ; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]] -; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]] +; MIPS64: beqz $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]] %bit = and i64 %a, 34359738368 %res = icmp ne i64 %bit, 0 br i1 %res, label %endif, label %if diff --git a/llvm/test/MC/Mips/cpsetup.s b/llvm/test/MC/Mips/cpsetup.s index c5d0f9b589c..149419f8a83 100644 --- a/llvm/test/MC/Mips/cpsetup.s +++ b/llvm/test/MC/Mips/cpsetup.s @@ -1,22 +1,22 @@ -# RUN: llvm-mc -triple mips64-unknown-linux -target-abi o32 -filetype=obj -o - %s | \ +# RUN: llvm-mc -triple mips-unknown-linux -target-abi o32 -filetype=obj -o - %s | \ # RUN: llvm-objdump -d -r - | FileCheck -check-prefixes=ALL,O32 %s -# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 %s | \ -# RUN: FileCheck -check-prefixes=ALL,ASM %s +# RUN: llvm-mc -triple mips-unknown-unknown -target-abi o32 %s | \ +# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-O32 %s # RUN: llvm-mc -triple mips64-unknown-linux -target-abi n32 -filetype=obj -o - %s | \ # RUN: llvm-objdump -d -r - | \ # RUN: FileCheck -check-prefixes=ALL,NXX,N32 %s # RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 %s | \ -# RUN: FileCheck -check-prefixes=ALL,ASM %s +# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N32 %s # RUN: llvm-mc -triple mips64-unknown-linux %s -filetype=obj -o - | \ # RUN: llvm-objdump -d -r - | \ # RUN: FileCheck -check-prefixes=ALL,NXX,N64 %s # RUN: llvm-mc -triple mips64-unknown-unknown %s | \ -# RUN: FileCheck -check-prefixes=ALL,ASM %s +# RUN: FileCheck -check-prefixes=ALL,ASM,ASM-N64 %s .text .option pic2 @@ -105,8 +105,10 @@ t3: # NXX-NEXT: nop # NXX-NEXT: sub $3, $3, $2 -# ASM: $tmp0: -# ASM-NEXT: .cpsetup $25, $2, $tmp0 +# ASM-O32: [[LABEL:\$tmp0]]: +# ASM-N32: [[LABEL:\.Ltmp0]]: +# ASM-N64: [[LABEL:\.Ltmp0]]: +# ASM-NEXT: .cpsetup $25, $2, [[LABEL]] # Ensure we have at least one instruction between labels so that the labels # we're matching aren't removed. diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s index f2ceca0f672..1cc47518314 100644 --- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s +++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s @@ -10,7 +10,7 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=micromips -show-encoding |\ # RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,O32-MICROMIPS -# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -mattr=micromips -show-encoding |\ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 -mattr=micromips -show-encoding |\ # RUN: FileCheck %s -check-prefixes=ALL,MICROMIPS,N32-MICROMIPS # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 -mattr=micromips -show-encoding |\ @@ -164,19 +164,19 @@ local_label: # N32: lw $25, %got_disp($tmp0)($gp) # encoding: [0x8f,0x99,A,A] # N32: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_Mips_GOT_DISP -# N64: ld $25, %got_disp($tmp0)($gp) # encoding: [0xdf,0x99,A,A] -# N64: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_Mips_GOT_DISP +# N64: ld $25, %got_disp(.Ltmp0)($gp) # encoding: [0xdf,0x99,A,A] +# N64: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_Mips_GOT_DISP # O32-MICROMIPS: lw $25, %got($tmp0)($gp) # encoding: [0xff,0x3c,A,A] # O32-MICROMIPS: # fixup A - offset: 0, value: %got($tmp0), kind: fixup_MICROMIPS_GOT16 # O32-MICROMIPS: addiu $25, $25, %lo($tmp0) # encoding: [0x33,0x39,A,A] # O32-MICROMIPS: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_MICROMIPS_LO16 -# N32-MICROMIPS: lw $25, %got_disp($tmp0)($gp) # encoding: [0xff,0x3c,A,A] -# N32-MICROMIPS: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_MICROMIPS_GOT_DISP +# N32-MICROMIPS: lw $25, %got_disp(.Ltmp0)($gp) # encoding: [0xff,0x3c,A,A] +# N32-MICROMIPS: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_MICROMIPS_GOT_DISP -# N64-MICROMIPS: ld $25, %got_disp($tmp0)($gp) # encoding: [0xdf,0x99,A,A] -# N64-MICROMIPS: # fixup A - offset: 0, value: %got_disp($tmp0), kind: fixup_MICROMIPS_GOT_DISP +# N64-MICROMIPS: ld $25, %got_disp(.Ltmp0)($gp) # encoding: [0xdf,0x99,A,A] +# N64-MICROMIPS: # fixup A - offset: 0, value: %got_disp(.Ltmp0), kind: fixup_MICROMIPS_GOT_DISP # NORMAL: jalr $25 # encoding: [0x03,0x20,0xf8,0x09] # MICROMIPS: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c] diff --git a/llvm/test/MC/Mips/macro-la.s b/llvm/test/MC/Mips/macro-la.s index cca4805054f..c419d64b391 100644 --- a/llvm/test/MC/Mips/macro-la.s +++ b/llvm/test/MC/Mips/macro-la.s @@ -1,11 +1,11 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ -# RUN: FileCheck %s +# RUN: FileCheck %s --check-prefixes=CHECK,O32 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | \ -# RUN: FileCheck %s +# RUN: FileCheck %s --check-prefixes=CHECK,O32 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 -target-abi=n32 | \ -# RUN: FileCheck %s +# RUN: FileCheck %s --check-prefixes=CHECK,N32 # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 -target-abi=n32 | \ -# RUN: FileCheck %s +# RUN: FileCheck %s --check-prefixes=CHECK,N32 # N64 should be acceptable too but we cannot convert la to dla yet. @@ -272,8 +272,12 @@ la $6, symbol+8($6) # CHECK: lui $1, %hi(symbol+8) # encoding: [0x3c,0x0 # CHECK: addiu $1, $1, %lo(symbol+8) # encoding: [0x24,0x21,A,A] # CHECK: # fixup A - offset: 0, value: %lo(symbol+8), kind: fixup_Mips_LO16 # CHECK: addu $6, $1, $6 # encoding: [0x00,0x26,0x30,0x21] -la $5, 1f # CHECK: lui $5, %hi($tmp0) # encoding: [0x3c,0x05,A,A] - # CHECK: # fixup A - offset: 0, value: %hi($tmp0), kind: fixup_Mips_HI16 - # CHECK: addiu $5, $5, %lo($tmp0) # encoding: [0x24,0xa5,A,A] - # CHECK: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16 +la $5, 1f # O32: lui $5, %hi($tmp0) # encoding: [0x3c,0x05,A,A] + # O32: # fixup A - offset: 0, value: %hi($tmp0), kind: fixup_Mips_HI16 + # O32: addiu $5, $5, %lo($tmp0) # encoding: [0x24,0xa5,A,A] + # O32: # fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16 + # N32: lui $5, %hi(.Ltmp0) # encoding: [0x3c,0x05,A,A] + # N32: # fixup A - offset: 0, value: %hi(.Ltmp0), kind: fixup_Mips_HI16 + # N32: addiu $5, $5, %lo(.Ltmp0) # encoding: [0x24,0xa5,A,A] + # N32: # fixup A - offset: 0, value: %lo(.Ltmp0), kind: fixup_Mips_LO16 1: diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s index bcc96b5aed1..d9f7729fd3f 100644 --- a/llvm/test/MC/Mips/mips3/valid.s +++ b/llvm/test/MC/Mips/mips3/valid.s @@ -112,8 +112,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index 0a4eb4d60cc..500560e99da 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -116,8 +116,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s index 270ff16c8a9..c60a91843d0 100644 --- a/llvm/test/MC/Mips/mips5/valid.s +++ b/llvm/test/MC/Mips/mips5/valid.s @@ -116,8 +116,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s index 0ba831b841b..b8c8a10e5de 100644 --- a/llvm/test/MC/Mips/mips64/valid.s +++ b/llvm/test/MC/Mips/mips64/valid.s @@ -123,8 +123,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index 5ae3adc46eb..7dd7289aece 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -136,8 +136,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index ab385daa96c..83681f69c44 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -136,8 +136,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index 39782f34f3a..e63ed1d78d8 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -137,8 +137,8 @@ a: floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 - j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] - # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 + j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A] + # CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26 j a # CHECK: j a # encoding: [0b000010AA,A,A,A] # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] |
