stop pattern matching 16-bit zero's of a register to MOV16r0,

instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.

llvm-svn: 91972

1 files changed, 10 insertions, 4 deletions

diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 3f09cb00958..c25e0ebd6bf 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -3700,15 +3700,21 @@ let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
 def MOV8r0   : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
                  "xor{b}\t$dst, $dst",
                  [(set GR8:$dst, 0)]>;
+                 
+ def MOV32r0  : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
+                  "xor{l}\t$dst, $dst",
+                  [(set GR32:$dst, 0)]>;
+
 // Use xorl instead of xorw since we don't care about the high 16 bits,
 // it's smaller, and it avoids a partial-register update.
 def MOV16r0  : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
-                 "", [(set GR16:$dst, 0)]>;
-def MOV32r0  : I<0x31, MRMInitReg,  (outs GR32:$dst), (ins),
-                 "xor{l}\t$dst, $dst",
-                 [(set GR32:$dst, 0)]>;
+                 "", [/*(set GR16:$dst, 0)*/]>;
 }
 
+let AddedComplexity = 1 in
+def : Pat<(i16 0),
+          (EXTRACT_SUBREG (MOV32r0), x86_subreg_16bit)>;
+
 //===----------------------------------------------------------------------===//
 // Thread Local Storage Instructions
 //