diff options
| author | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-10-03 18:29:01 +0000 |
|---|---|---|
| committer | Konstantin Zhuravlyov <kzhuravl_dev@outlook.com> | 2016-10-03 18:29:01 +0000 |
| commit | 691e2e020b1b67defd5c2a3f7c5cf0d76056b10a (patch) | |
| tree | db30905b1751a44682fb76eae5372590503b3715 | |
| parent | b4d2678c6f2c8e411bd2f59e58667a3a1921ae8a (diff) | |
| download | bcm5719-llvm-691e2e020b1b67defd5c2a3f7c5cf0d76056b10a.tar.gz bcm5719-llvm-691e2e020b1b67defd5c2a3f7c5cf0d76056b10a.zip | |
[AMDGPU] Sign extend AShr when promoting (instead of zero extending)
llvm-svn: 283130
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll | 16 |
2 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index 843001ae0f1..88b1be2e6b8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -172,8 +172,8 @@ bool AMDGPUCodeGenPrepare::isI32Ty(const Type *T) const { } bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const { - return I.getOpcode() == Instruction::SDiv || - I.getOpcode() == Instruction::SRem; + return I.getOpcode() == Instruction::AShr || + I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem; } bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const { diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll index ed512b4ddd9..a4a882ed844 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll @@ -226,8 +226,8 @@ define i16 @lshr_exact_i16(i16 %a, i16 %b) { } ; VI-LABEL: @ashr_i16( -; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 -; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32 +; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32 +; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32 ; VI: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]] ; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI: ret i16 %[[R_16]] @@ -237,8 +237,8 @@ define i16 @ashr_i16(i16 %a, i16 %b) { } ; VI-LABEL: @ashr_exact_i16( -; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 -; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32 +; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32 +; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32 ; VI: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]] ; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 ; VI: ret i16 %[[R_16]] @@ -651,8 +651,8 @@ define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) { } ; VI-LABEL: @ashr_3xi16( -; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> -; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> +; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32> +; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32> ; VI: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]] ; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> ; VI: ret <3 x i16> %[[R_16]] @@ -662,8 +662,8 @@ define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) { } ; VI-LABEL: @ashr_exact_3xi16( -; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> -; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> +; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32> +; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32> ; VI: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]] ; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> ; VI: ret <3 x i16> %[[R_16]] |
