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authorChris Lattner <sabre@nondot.org>2006-07-18 19:27:30 +0000
committerChris Lattner <sabre@nondot.org>2006-07-18 19:27:30 +0000
commit68ee5cfe1015ba369a361431c83cb2b6b519cc9c (patch)
treedd45dff3fecb8ade6386121068a0b099c9e4ecee
parente9c68f52e1651f4ea36ddd1d299db73414a0a609 (diff)
downloadbcm5719-llvm-68ee5cfe1015ba369a361431c83cb2b6b519cc9c.tar.gz
bcm5719-llvm-68ee5cfe1015ba369a361431c83cb2b6b519cc9c.zip
Fix case where identical cases were not detected across case #0, because
instructions not handled would have a case value of #0, throwing things off. This marginally shrinks the X86 asmprinter, but shrinks the sparc asmwriter by 25 lines. llvm-svn: 29187
-rw-r--r--llvm/utils/TableGen/AsmWriterEmitter.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index d8e98394078..2cf16e797c6 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -332,7 +332,7 @@ void AsmWriterEmitter::
FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
std::vector<unsigned> &InstIdxs,
std::vector<unsigned> &InstOpsUsed) const {
- InstIdxs.assign(NumberedInstructions.size(), 0);
+ InstIdxs.assign(NumberedInstructions.size(), ~0U);
// This vector parallels UniqueOperandCommands, keeping track of which
// instructions each case are used for. It is a comma separated string of
@@ -551,7 +551,8 @@ void AsmWriterEmitter::run(std::ostream &O) {
// Otherwise, we can include this in the initial lookup table. Add it in.
BitsLeft -= NumBits;
for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
- OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
+ if (InstIdxs[i] != ~0U)
+ OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
// Remove the info about this operand.
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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