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authorMatt Arsenault <Matthew.Arsenault@amd.com>2018-03-17 15:17:45 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2018-03-17 15:17:45 +0000
commit685d1e81577dcbf84eda0923699f58b4fc362379 (patch)
tree4f888bd00d7069657e5664c913365be321ad7c3b
parent85803366d6dac06f32dee66c9fcd17b51cf3b3e3 (diff)
downloadbcm5719-llvm-685d1e81577dcbf84eda0923699f58b4fc362379.tar.gz
bcm5719-llvm-685d1e81577dcbf84eda0923699f58b4fc362379.zip
AMDGPU/GlobalISel: Basic G_GEP legality
llvm-svn: 327773
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp22
-rw-r--r--llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-gep.mir92
2 files changed, 110 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 283de3b31da..9c8941c2fdc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -32,6 +32,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
};
+ auto AMDGPUAS = ST.getAMDGPUAS();
+
const LLT S1 = LLT::scalar(1);
const LLT V2S16 = LLT::vector(2, 16);
@@ -40,7 +42,17 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
-
+ const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
+ const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS.FLAT_ADDRESS);
+ const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS.PRIVATE_ADDRESS);
+
+ const LLT AddrSpaces[] = {
+ GlobalPtr,
+ ConstantPtr,
+ LocalPtr,
+ FlatPtr,
+ PrivatePtr
+ };
setAction({G_ADD, S32}, Legal);
setAction({G_MUL, S32}, Legal);
@@ -84,9 +96,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
setAction({G_FPTOUI, S32}, Legal);
setAction({G_FPTOUI, 1, S32}, Legal);
- setAction({G_GEP, GlobalPtr}, Legal);
- setAction({G_GEP, ConstantPtr}, Legal);
- setAction({G_GEP, 1, S64}, Legal);
+ for (LLT PtrTy : AddrSpaces) {
+ LLT IdxTy = LLT::scalar(PtrTy.getSizeInBits());
+ setAction({G_GEP, PtrTy}, Legal);
+ setAction({G_GEP, 1, IdxTy}, Legal);
+ }
setAction({G_ICMP, S1}, Legal);
setAction({G_ICMP, 1, S32}, Legal);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-gep.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-gep.mir
new file mode 100644
index 00000000000..05afb68accc
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-gep.mir
@@ -0,0 +1,92 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_gep_global_i64_idx
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_gep_global_i64_idx
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[GEP:%[0-9]+]]:_(p1) = G_GEP [[COPY]], [[COPY1]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[GEP]](p1)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(p1) = G_GEP %0, %1
+
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_gep_flat_i64_idx
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_gep_flat_i64_idx
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[COPY1]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[GEP]](p0)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(p0) = G_GEP %0, %1
+
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_gep_constant_i64_idx
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+ ; CHECK-LABEL: name: test_gep_constant_i64_idx
+ ; CHECK: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; CHECK: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[COPY1]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[GEP]](p4)
+ %0:_(p4) = COPY $vgpr0_vgpr1
+ %1:_(s64) = COPY $vgpr2_vgpr3
+ %2:_(p4) = G_GEP %0, %1
+
+ $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name: test_gep_local_i32_idx
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_gep_local_i32_idx
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[GEP:%[0-9]+]]:_(p3) = G_GEP [[COPY]], [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[GEP]](p3)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(p3) = G_GEP %0, %1
+
+ $vgpr0 = COPY %2
+...
+
+---
+name: test_gep_private_i32_idx
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; CHECK-LABEL: name: test_gep_private_i32_idx
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK: [[GEP:%[0-9]+]]:_(p5) = G_GEP [[COPY]], [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[GEP]](p5)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(p5) = G_GEP %0, %1
+
+ $vgpr0 = COPY %2
+...
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