MachineScheduler/ScheduleDAG: Add support to skipping a node.

The DAG mutators in the scheduler cannot really remove DAG nodes as
additional anlysis information such as ScheduleDAGToplogicalSort are
already computed at this point and rely on a fixed number of DAG nodes.

Alleviate the missing removal with a new flag: Setting the new skip
flag on a node ignores it during scheduling.

llvm-svn: 286655

3 files changed, 15 insertions, 3 deletions

diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index ed4e0bc8a4a..feb647baa30 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -289,6 +289,7 @@ namespace llvm {
     bool isCloned         : 1;          // True if this node has been cloned.
     bool isUnbuffered     : 1;          // Uses an unbuffered resource.
     bool hasReservedResource : 1;       // Uses a reserved resource.
+    bool skip             : 1;          ///< Ignore/Skip this node.
     Sched::Preference SchedulingPref;   // Scheduling preference.
 
   private:
@@ -314,7 +315,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false),
+        isUnbuffered(false), hasReservedResource(false), skip(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@@ -330,7 +331,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false),
+        isUnbuffered(false), hasReservedResource(false), skip(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@@ -345,7 +346,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false),
+        isUnbuffered(false), hasReservedResource(false), skip(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 3984a15861d..f7dd53b9b9b 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -707,6 +707,7 @@ void ScheduleDAGMI::schedule() {
     DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
     SUnit *SU = SchedImpl->pickNode(IsTopNode);
     if (!SU) break;
+    assert(!SU->skip);
 
     assert(!SU->isScheduled && "Node already scheduled");
     if (!checkSchedLimit())
@@ -764,6 +765,8 @@ findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
                       SmallVectorImpl<SUnit*> &BotRoots) {
   for (std::vector<SUnit>::iterator
          I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
+    if (I->skip)
+      continue;
     SUnit *SU = &(*I);
     assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
 
@@ -1518,6 +1521,8 @@ void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
   SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
   for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
     SUnit *SU = &DAG->SUnits[Idx];
+    if (SU->skip)
+      continue;
     if ((IsLoad && !SU->getInstr()->mayLoad()) ||
         (!IsLoad && !SU->getInstr()->mayStore()))
       continue;
@@ -1810,6 +1815,8 @@ void CopyConstrain::apply(ScheduleDAGInstrs *DAGInstrs) {
 
   for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
     SUnit *SU = &DAG->SUnits[Idx];
+    if (SU->skip)
+      continue;
     if (!SU->getInstr()->isCopy())
       continue;
 
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
index 1f0c3283ceb..bb118628fb0 100644
--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -329,6 +329,10 @@ void SUnit::dump(const ScheduleDAG *G) const {
 
 void SUnit::dumpAll(const ScheduleDAG *G) const {
   dump(G);
+  if (skip) {
+    dbgs() << "  Skipped\n";
+    return;
+  }
 
   dbgs() << "  # preds left       : " << NumPredsLeft << "\n";
   dbgs() << "  # succs left       : " << NumSuccsLeft << "\n";