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| author | Craig Topper <craig.topper@intel.com> | 2018-02-25 06:21:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-25 06:21:04 +0000 |
| commit | 6694df14e6331b26b7a2aa9f6e9f708e1ef4f8e0 (patch) | |
| tree | 064bc47794e78a57f5757edccfdadc43486aba62 | |
| parent | 2d836470077a244b2fda6edd50360a3d41d426d4 (diff) | |
| download | bcm5719-llvm-6694df14e6331b26b7a2aa9f6e9f708e1ef4f8e0.tar.gz bcm5719-llvm-6694df14e6331b26b7a2aa9f6e9f708e1ef4f8e0.zip | |
[X86] Use SDNode instead of SDPatternOperator. NFC
llvm-svn: 326048
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 7b17ab322e9..9fc9a7dcb72 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8450,7 +8450,7 @@ def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))), multiclass avx512_extend_common<bits<8> opc, string OpcodeStr, OpndItins itins, X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo, - X86MemOperand x86memop, PatFrag LdFrag, SDPatternOperator OpNode>{ + X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{ let ExeDomain = DestInfo.ExeDomain in { defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst), (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src", @@ -8465,7 +8465,7 @@ multiclass avx512_extend_common<bits<8> opc, string OpcodeStr, OpndItins itins, } multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> { let Predicates = [HasVLX, HasBWI] in { defm Z128: avx512_extend_common<opc, OpcodeStr, itins, v8i16x_info, @@ -8484,7 +8484,7 @@ multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, } multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> { let Predicates = [HasVLX, HasAVX512] in { defm Z128: avx512_extend_common<opc, OpcodeStr, itins, v4i32x_info, @@ -8503,7 +8503,7 @@ multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, } multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> { let Predicates = [HasVLX, HasAVX512] in { defm Z128: avx512_extend_common<opc, OpcodeStr, itins, v2i64x_info, @@ -8522,7 +8522,7 @@ multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, } multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> { let Predicates = [HasVLX, HasAVX512] in { defm Z128: avx512_extend_common<opc, OpcodeStr, itins, v4i32x_info, @@ -8541,7 +8541,7 @@ multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, } multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> { let Predicates = [HasVLX, HasAVX512] in { defm Z128: avx512_extend_common<opc, OpcodeStr, itins, v2i64x_info, @@ -8560,7 +8560,7 @@ multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, } multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, - SDPatternOperator OpNode, SDPatternOperator InVecNode, string ExtTy, + SDNode OpNode, SDNode InVecNode, string ExtTy, OpndItins itins, PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> { let Predicates = [HasVLX, HasAVX512] in { |
