diff options
| author | Tim Northover <tnorthover@apple.com> | 2016-08-24 15:37:51 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-08-24 15:37:51 +0000 |
| commit | 65f6336ff94c1e707cf9f0960a53b426c65cfca2 (patch) | |
| tree | 4087420d07783e7d7ad22e85d3682be7f892462e | |
| parent | 1006ca7176f412d3353d34c5ad963c1680a4e60e (diff) | |
| download | bcm5719-llvm-65f6336ff94c1e707cf9f0960a53b426c65cfca2.tar.gz bcm5719-llvm-65f6336ff94c1e707cf9f0960a53b426c65cfca2.zip | |
GlobalISel: fix cmp test to be in SSA form
llvm-svn: 279633
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir index 9aa7a68324f..d2be05a7849 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir @@ -19,32 +19,33 @@ registers: - { id: 4, class: _ } - { id: 5, class: _ } - { id: 6, class: _ } + - { id: 7, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 %0(64) = COPY %x0 %1(64) = COPY %x0 - %4(8) = G_TRUNC { s8, s64 } %0 - %5(8) = G_TRUNC { s8, s64 } %1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 ; CHECK: [[TST32:%[0-9]+]](32) = G_ICMP { s32, s64 } intpred(sge), %0, %1 - ; CHECK: %2(1) = G_TRUNC { s1, s32 } [[TST32]] - %2(1) = G_ICMP { s1, s64 } intpred(sge), %0, %1 - - ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %4 - ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %5 - ; CHECK: %3(32) = G_ICMP { s32, s32 } intpred(ne), [[LHS32]], [[RHS32]] - %3(32) = G_ICMP { s32, s8 } intpred(ne), %4, %5 - - ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %4 - ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %5 - ; CHECK: %3(32) = G_ICMP { s32, s32 } intpred(ugt), [[LHS32]], [[RHS32]] - %3(32) = G_ICMP { s32, s8 } intpred(ugt), %4, %5 - - ; CHECK: [[LHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %4 - ; CHECK: [[RHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %5 - ; CHECK: %6(32) = G_ICMP { s32, s32 } intpred(sle), [[LHS32]], [[RHS32]] - %6(32) = G_ICMP { s32, s8 } intpred(sle), %4, %5 + ; CHECK: %4(1) = G_TRUNC { s1, s32 } [[TST32]] + %4(1) = G_ICMP { s1, s64 } intpred(sge), %0, %1 + + ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %2 + ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %3 + ; CHECK: %5(32) = G_ICMP { s32, s32 } intpred(ne), [[LHS32]], [[RHS32]] + %5(32) = G_ICMP { s32, s8 } intpred(ne), %2, %3 + + ; CHECK: [[LHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %2 + ; CHECK: [[RHS32:%[0-9]+]](32) = G_ZEXT { s32, s8 } %3 + ; CHECK: %6(32) = G_ICMP { s32, s32 } intpred(ugt), [[LHS32]], [[RHS32]] + %6(32) = G_ICMP { s32, s8 } intpred(ugt), %2, %3 + + ; CHECK: [[LHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %2 + ; CHECK: [[RHS32:%[0-9]+]](32) = G_SEXT { s32, s8 } %3 + ; CHECK: %7(32) = G_ICMP { s32, s32 } intpred(sle), [[LHS32]], [[RHS32]] + %7(32) = G_ICMP { s32, s8 } intpred(sle), %2, %3 ... |
