Allow strict subclasses of register classes, this way we can handle

ARM instructions with:

foo GPR, rGPR

which happens a lot.

llvm-svn: 112025

1 files changed, 3 insertions, 2 deletions

diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index 243208612d5..6c16fcfaa8a 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -112,9 +112,10 @@ struct OperandsSignature {
       if (!RC)
         return false;
 
-      // For now, all the operands must have the same register class.
+      // For now, all the operands must have the same register class or be
+      // a strict subclass of the destination.
       if (DstRC) {
-        if (DstRC != RC)
+        if (DstRC != RC && !DstRC->hasSubClass(RC))
           return false;
       } else
         DstRC = RC;