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| author | Chris Lattner <sabre@nondot.org> | 2003-09-10 19:52:54 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-09-10 19:52:54 +0000 |
| commit | 632cccf6460a3472b8bc09d2d5c094b395bf57a2 (patch) | |
| tree | fe34a8b25dd502299294e10ed9cc755e4c2394e6 | |
| parent | 59068a0d713d9a8d540d06dde8316d7cf47e1da3 (diff) | |
| download | bcm5719-llvm-632cccf6460a3472b8bc09d2d5c094b395bf57a2.tar.gz bcm5719-llvm-632cccf6460a3472b8bc09d2d5c094b395bf57a2.zip | |
Be a little more specific about what is begin generated. Only print
command line if VERBOSE=1
llvm-svn: 8453
| -rw-r--r-- | llvm/lib/Target/X86/Makefile | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/Makefile b/llvm/lib/Target/X86/Makefile index 84f168a9371..87522ec5d3b 100644 --- a/llvm/lib/Target/X86/Makefile +++ b/llvm/lib/Target/X86/Makefile @@ -8,28 +8,28 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \ X86GenInstrInfo.inc X86GenInstrSelector.inc X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ + @echo "Building $< register names with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ + @echo "Building $< register information header with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ + @echo "Building $< register information implementation with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ + @echo "Building $< instruction names with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ + @echo "Building $< instruction information with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN) - @echo "Tblgen'ing $<" - $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ + @echo "Building $< instruction selector with tblgen" + $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@ clean:: $(VERB) rm -f *.inc |
