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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-28 00:34:17 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-28 00:34:17 +0000 |
| commit | 62005d69a70ed57c8b3d24b5fb19454559a0d288 (patch) | |
| tree | f13aa170dcf38b70e01ef1ef825af50d962531df | |
| parent | 3425710ccaaaddb0c855f6af5bc47784db15c391 (diff) | |
| download | bcm5719-llvm-62005d69a70ed57c8b3d24b5fb19454559a0d288.tar.gz bcm5719-llvm-62005d69a70ed57c8b3d24b5fb19454559a0d288.zip | |
[mips] Set isAllocatable and CoveredBySubRegs.
llvm-svn: 189430
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index 022a9c0c7ba..22c489090d8 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -60,6 +60,7 @@ class AFPR<bits<16> Enc, string n, list<Register> subregs> class AFPR64<bits<16> Enc, string n, list<Register> subregs> : MipsRegWithSubRegs<Enc, n, subregs> { let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; } // Mips 128-bit (aliased) MSA Registers @@ -294,7 +295,8 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // * FGR32 - 32 32-bit registers (single float only mode) def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; -def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>; +def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, + Unallocatable; def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments |
