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author | Peter Collingbourne <peter@pcc.me.uk> | 2011-04-29 18:47:25 +0000 |
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committer | Peter Collingbourne <peter@pcc.me.uk> | 2011-04-29 18:47:25 +0000 |
commit | 61f6602acd523b37d76b5cce2987ee3f680d750a (patch) | |
tree | d5e7d4e3d8cf50d2e69e40cc7ef1f737da009b6b | |
parent | 73ad5bc9ea0b6dad8392800fbe863bd34ab79c69 (diff) | |
download | bcm5719-llvm-61f6602acd523b37d76b5cce2987ee3f680d750a.tar.gz bcm5719-llvm-61f6602acd523b37d76b5cce2987ee3f680d750a.zip |
SimplifyCFG: Add Trunc, ZExt and SExt to the list of cheap instructions for phi node folding
llvm-svn: 130526
-rw-r--r-- | llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 3 | ||||
-rw-r--r-- | llvm/test/Transforms/SimplifyCFG/PhiEliminate2.ll | 15 |
2 files changed, 12 insertions, 6 deletions
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 5177d339597..1bddecb8c40 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -261,6 +261,9 @@ static bool DominatesMergePoint(Value *V, BasicBlock *BB, case Instruction::LShr: case Instruction::AShr: case Instruction::ICmp: + case Instruction::Trunc: + case Instruction::ZExt: + case Instruction::SExt: break; // These are all cheap and non-trapping instructions. } diff --git a/llvm/test/Transforms/SimplifyCFG/PhiEliminate2.ll b/llvm/test/Transforms/SimplifyCFG/PhiEliminate2.ll index c0f6781293d..0b3893d520d 100644 --- a/llvm/test/Transforms/SimplifyCFG/PhiEliminate2.ll +++ b/llvm/test/Transforms/SimplifyCFG/PhiEliminate2.ll @@ -1,14 +1,17 @@ ; RUN: opt < %s -simplifycfg -S | not grep br -define i32 @test(i1 %C, i32 %V1, i32 %V2) { +define i32 @test(i1 %C, i32 %V1, i32 %V2, i16 %V3) { entry: - br i1 %C, label %then, label %Cont + br i1 %C, label %then, label %else then: ; preds = %entry - %V3 = or i32 %V2, %V1 ; <i32> [#uses=1] + %V4 = or i32 %V2, %V1 ; <i32> [#uses=1] br label %Cont -Cont: ; preds = %then, %entry - %V4 = phi i32 [ %V1, %entry ], [ %V3, %then ] ; <i32> [#uses=0] - call i32 @test( i1 false, i32 0, i32 0 ) ; <i32>:0 [#uses=0] +else: ; preds = %entry + %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1] + br label %Cont +Cont: ; preds = %then, %else + %V6 = phi i32 [ %V5, %else ], [ %V4, %then ] ; <i32> [#uses=0] + call i32 @test( i1 false, i32 0, i32 0, i16 0 ) ; <i32>:0 [#uses=0] ret i32 %V1 } |