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author | Philip Reames <listmail@philipreames.com> | 2019-02-14 17:01:15 +0000 |
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committer | Philip Reames <listmail@philipreames.com> | 2019-02-14 17:01:15 +0000 |
commit | 617cd10bf73e03e0043a0b8c3bf8088a275de038 (patch) | |
tree | 9efaa25e424a562000177e06a0b1c51c8e10d591 | |
parent | c39f8dfa7317f10923cf5ab2d650adde1abaa612 (diff) | |
download | bcm5719-llvm-617cd10bf73e03e0043a0b8c3bf8088a275de038.tar.gz bcm5719-llvm-617cd10bf73e03e0043a0b8c3bf8088a275de038.zip |
[Tests] Add tests for all idemptotent atomicrmws
Base for a followup patch to strengthen the InstCombine transform, and then integrate the ExpandAtomics logic.
llvm-svn: 354036
-rw-r--r-- | llvm/test/Transforms/InstCombine/atomicrmw.ll | 68 |
1 files changed, 62 insertions, 6 deletions
diff --git a/llvm/test/Transforms/InstCombine/atomicrmw.ll b/llvm/test/Transforms/InstCombine/atomicrmw.ll index e9474f1685c..71eba4f5459 100644 --- a/llvm/test/Transforms/InstCombine/atomicrmw.ll +++ b/llvm/test/Transforms/InstCombine/atomicrmw.ll @@ -12,6 +12,62 @@ define i32 @atomic_add_zero(i32* %addr) { ret i32 %res } +; CHECK-LABEL: atomic_or_zero +; CHECK-NEXT: %res = load atomic i32, i32* %addr monotonic, align 4 +; CHECK-NEXT: ret i32 %res +define i32 @atomic_or_zero(i32* %addr) { + %res = atomicrmw add i32* %addr, i32 0 monotonic + ret i32 %res +} + +; CHECK-LABEL: atomic_sub_zero +; CHECK-NEXT: %res = load atomic i32, i32* %addr monotonic, align 4 +; CHECK-NEXT: ret i32 %res +define i32 @atomic_sub_zero(i32* %addr) { + %res = atomicrmw sub i32* %addr, i32 0 monotonic + ret i32 %res +} + +; CHECK-LABEL: atomic_and_allones +; CHECK-NEXT: %res = atomicrmw and i32* %addr, i32 -1 monotonic +; CHECK-NEXT: ret i32 %res +define i32 @atomic_and_allones(i32* %addr) { + %res = atomicrmw and i32* %addr, i32 -1 monotonic + ret i32 %res +} +; CHECK-LABEL: atomic_umin_uint_max +; CHECK-NEXT: %res = atomicrmw umin i32* %addr, i32 -1 monotonic +; CHECK-NEXT: ret i32 %res +define i32 @atomic_umin_uint_max(i32* %addr) { + %res = atomicrmw umin i32* %addr, i32 -1 monotonic + ret i32 %res +} + +; CHECK-LABEL: atomic_umax_zero +; CHECK-NEXT: %res = atomicrmw umax i32* %addr, i32 0 monotonic +; CHECK-NEXT: ret i32 %res +define i32 @atomic_umax_zero(i32* %addr) { + %res = atomicrmw umax i32* %addr, i32 0 monotonic + ret i32 %res +} + +; CHECK-LABEL: atomic_min_smax_char +; CHECK-NEXT: %res = atomicrmw min i8* %addr, i8 -128 monotonic +; CHECK-NEXT: ret i8 %res +define i8 @atomic_min_smax_char(i8* %addr) { + %res = atomicrmw min i8* %addr, i8 -128 monotonic + ret i8 %res +} + +; CHECK-LABEL: atomic_max_smin_char +; CHECK-NEXT: %res = atomicrmw max i8* %addr, i8 127 monotonic +; CHECK-NEXT: ret i8 %res +define i8 @atomic_max_smin_char(i8* %addr) { + %res = atomicrmw max i8* %addr, i8 127 monotonic + ret i8 %res +} + + ; Don't transform volatile atomicrmw. This would eliminate a volatile store ; otherwise. ; CHECK-LABEL: atomic_sub_zero_volatile @@ -24,10 +80,10 @@ define i64 @atomic_sub_zero_volatile(i64* %addr) { ; Check that the transformation properly preserve the syncscope. -; CHECK-LABEL: atomic_or_zero +; CHECK-LABEL: atomic_syncscope ; CHECK-NEXT: %res = load atomic i16, i16* %addr syncscope("some_syncscope") acquire, align 2 ; CHECK-NEXT: ret i16 %res -define i16 @atomic_or_zero(i16* %addr) { +define i16 @atomic_syncscope(i16* %addr) { %res = atomicrmw or i16* %addr, i16 0 syncscope("some_syncscope") acquire ret i16 %res } @@ -45,11 +101,11 @@ define i16 @atomic_or_zero_seq_cst(i16* %addr) { ; Check that the transformation does not apply when the value is changed by ; the atomic operation (non zero constant). -; CHECK-LABEL: atomic_or_non_zero -; CHECK-NEXT: %res = atomicrmw or i16* %addr, i16 2 monotonic +; CHECK-LABEL: atomic_add_non_zero +; CHECK-NEXT: %res = atomicrmw add i16* %addr, i16 2 monotonic ; CHECK-NEXT: ret i16 %res -define i16 @atomic_or_non_zero(i16* %addr) { - %res = atomicrmw or i16* %addr, i16 2 monotonic +define i16 @atomic_add_non_zero(i16* %addr) { + %res = atomicrmw add i16* %addr, i16 2 monotonic ret i16 %res } |