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| author | Luis Marques <luismarques@lowrisc.org> | 2019-03-26 12:55:00 +0000 |
|---|---|---|
| committer | Luis Marques <luismarques@lowrisc.org> | 2019-03-26 12:55:00 +0000 |
| commit | 614fd9d830ce1449d197fb16c4a656e65ca238a2 (patch) | |
| tree | a45e3031a0318b68ac4ce6ac1f1b5e640f4dfe62 | |
| parent | e24441aab03e393d591d9252612e8c0ac557b1c3 (diff) | |
| download | bcm5719-llvm-614fd9d830ce1449d197fb16c4a656e65ca238a2.tar.gz bcm5719-llvm-614fd9d830ce1449d197fb16c4a656e65ca238a2.zip | |
[RISCV] Improve codegen for icmp {ne,eq} with a constant
Adds two patterns to improve the codegen of GPR value comparisons with small
constants. Instead of first loading the constant into another register and then
doing an XOR of those registers, these patterns directly use the constant as an
XORI immediate.
llvm-svn: 356990
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/i32-icmp.ll | 22 |
2 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 296e736ab10..dce704cce10 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -771,8 +771,12 @@ def : PatGprSimm12<setult, SLTIU>; // handled by a RISC-V instruction. def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>; def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; +def : Pat<(seteq GPR:$rs1, simm12:$imm12), + (SLTIU (XORI GPR:$rs1, simm12:$imm12), 1)>; def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; +def : Pat<(setne GPR:$rs1, simm12:$imm12), + (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>; def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll index 3b89504bbc0..04b1eeaad21 100644 --- a/llvm/test/CodeGen/RISCV/i32-icmp.ll +++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll @@ -16,6 +16,17 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind { ret i32 %2 } +define i32 @icmp_eq_constant(i32 %a) nounwind { +; RV32I-LABEL: icmp_eq_constant: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a0, a0, 42 +; RV32I-NEXT: seqz a0, a0 +; RV32I-NEXT: ret + %1 = icmp eq i32 %a, 42 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_eqz(i32 %a) nounwind { ; RV32I-LABEL: icmp_eqz: ; RV32I: # %bb.0: @@ -37,6 +48,17 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind { ret i32 %2 } +define i32 @icmp_ne_constant(i32 %a) nounwind { +; RV32I-LABEL: icmp_ne_constant: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a0, a0, 42 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: ret + %1 = icmp ne i32 %a, 42 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_nez(i32 %a) nounwind { ; RV32I-LABEL: icmp_nez: ; RV32I: # %bb.0: |
