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author | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-02-20 15:05:19 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@quicinc.com> | 2019-02-20 15:05:19 +0000 |
commit | 6128ac5a8fbb890193168caf1896d4c3e16c36ca (patch) | |
tree | 29123a0375d07b7589d476e780632c34bbd232c8 | |
parent | 8df4fbc5a70fd035e66497b964b4bc2779924e61 (diff) | |
download | bcm5719-llvm-6128ac5a8fbb890193168caf1896d4c3e16c36ca.tar.gz bcm5719-llvm-6128ac5a8fbb890193168caf1896d4c3e16c36ca.zip |
[Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND
llvm-svn: 354473
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 5 | ||||
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll | 16 |
3 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index d34d189ceaf..605fcfc2555 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -848,6 +848,9 @@ void HexagonDAGToDAGISel::SelectD2P(SDNode *N) { void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) { const SDLoc &dl(N); MVT ResTy = N->getValueType(0).getSimpleVT(); + // The argument to V2Q should be a single vector. + MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; + assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits()); SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32); SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C); @@ -859,6 +862,8 @@ void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) { void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) { const SDLoc &dl(N); MVT ResTy = N->getValueType(0).getSimpleVT(); + // The result of V2Q should be a single vector. + assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits()); SDValue C = CurDAG->getTargetConstant(-1, dl, MVT::i32); SDNode *R = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, C); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 6ab35c39bd4..345c657787a 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1541,6 +1541,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SRL: case ISD::SETCC: case ISD::VSELECT: + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND_INREG: return SplitHvxPairOp(Op, DAG); } diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll new file mode 100644 index 00000000000..e2fa59b3e22 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Make sure that this doesn't crash. +; CHECK: vadd + +define void @foo(<64 x i32>* %a0, <64 x i32>* %a1) #0 { + %v0 = load <64 x i32>, <64 x i32>* %a0, align 128 + %v1 = load <64 x i32>, <64 x i32>* %a1, align 128 + %v2 = icmp sgt <64 x i32> %v0, zeroinitializer + %v3 = sext <64 x i1> %v2 to <64 x i32> + %v4 = add nsw <64 x i32> %v1, %v3 + store <64 x i32> %v4, <64 x i32>* %a1, align 128 + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b" } |