diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-21 23:23:05 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-21 23:23:05 +0000 |
| commit | 60ba03e2103a7c39d89e712652fb8d10467802c4 (patch) | |
| tree | ea07e2795ba5450512401d9352d4be5242badf1e | |
| parent | 31c69a3d6363463c08b86914c0c8cfc5c929c37e (diff) | |
| download | bcm5719-llvm-60ba03e2103a7c39d89e712652fb8d10467802c4.tar.gz bcm5719-llvm-60ba03e2103a7c39d89e712652fb8d10467802c4.zip | |
AMDGPU: Fix not marking new gfx10 SGPRs as CSRs
llvm-svn: 361330
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/csr-gfx10.ll | 15 |
2 files changed, 18 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td index 8389058e3f7..8fdb97500ca 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td @@ -110,12 +110,12 @@ def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs< (sequence "VGPR%u", 32, 255) >; -def CSR_AMDGPU_SGPRs_32_103 : CalleeSavedRegs< - (sequence "SGPR%u", 32, 103) +def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs< + (sequence "SGPR%u", 32, 105) >; def CSR_AMDGPU_HighRegs : CalleeSavedRegs< - (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_103) + (add CSR_AMDGPU_VGPRs_32_255, CSR_AMDGPU_SGPRs_32_105) >; // Calling convention for leaf functions diff --git a/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll b/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll new file mode 100644 index 00000000000..17855568ed9 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/csr-gfx10.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s + +; Make sure new higher SGPRs are callee saved +; GFX10-LABEL: {{^}}callee_new_sgprs: +; GFX10: v_writelane_b32 v0, s104, 0 +; GFX10: v_writelane_b32 v0, s105, 1 +; GFX10: ; clobber s104 +; GFX10: ; clobber s105 +; GFX10: v_readlane_b32 s105, v0, 1 +; GFX10: v_readlane_b32 s104, v0, 0 +define void @callee_new_sgprs() { + call void asm sideeffect "; clobber s104", "~{s104}"() + call void asm sideeffect "; clobber s105", "~{s105}"() + ret void +} |
