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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-26 13:48:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-26 13:48:04 +0000 |
| commit | 5f798f134659e7917cbca89702111b13d50e5b46 (patch) | |
| tree | 61d3bc54061b04f9f5519bad9becbe1d38261fbb | |
| parent | e0b84434606117cf765c066d232626271591fe96 (diff) | |
| download | bcm5719-llvm-5f798f134659e7917cbca89702111b13d50e5b46.tar.gz bcm5719-llvm-5f798f134659e7917cbca89702111b13d50e5b46.zip | |
AMDGPU: Fix unused variable
llvm-svn: 364426
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 72ce01504fc..098152b23aa 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -526,7 +526,6 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST, static unsigned findScratchNonCalleeSaveRegister(MachineFunction &MF, LivePhysRegs &LiveRegs, const TargetRegisterClass &RC) { - const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); MachineRegisterInfo &MRI = MF.getRegInfo(); // Mark callee saved registers as used so we will not choose them. |
