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authorKrzysztof Parzyszek <kparzysz@quicinc.com>2019-02-21 18:39:22 +0000
committerKrzysztof Parzyszek <kparzysz@quicinc.com>2019-02-21 18:39:22 +0000
commit5f47fac3a2b026834e1bde04e60e8f82f4314b6e (patch)
treece16e92117733010f31332bcfde4f96489464b2e
parent04661e1084cc76bc6b88e5d13d7c91f4b1044f27 (diff)
downloadbcm5719-llvm-5f47fac3a2b026834e1bde04e60e8f82f4314b6e.tar.gz
bcm5719-llvm-5f47fac3a2b026834e1bde04e60e8f82f4314b6e.zip
[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap
The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. llvm-svn: 354606
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp32
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPatterns.td2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPseudo.td5
-rw-r--r--llvm/test/CodeGen/Hexagon/trap-crash.ll20
-rw-r--r--llvm/test/CodeGen/Hexagon/trap-unreachable.ll4
5 files changed, 61 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index b0b029682bf..68e4adec081 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1313,6 +1313,38 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
return true;
}
+ case Hexagon::PS_crash: {
+ // Generate a misaligned load that is guaranteed to cause a crash.
+ class CrashPseudoSourceValue : public PseudoSourceValue {
+ public:
+ CrashPseudoSourceValue(const TargetInstrInfo &TII)
+ : PseudoSourceValue(TargetCustom, TII) {}
+
+ bool isConstant(const MachineFrameInfo *) const override {
+ return false;
+ }
+ bool isAliased(const MachineFrameInfo *) const override {
+ return false;
+ }
+ bool mayAlias(const MachineFrameInfo *) const override {
+ return false;
+ }
+ void printCustom(raw_ostream &OS) const override {
+ OS << "MisalignedCrash";
+ }
+ };
+
+ static const CrashPseudoSourceValue CrashPSV(*this);
+ MachineMemOperand *MMO = MF.getMachineMemOperand(
+ MachinePointerInfo(&CrashPSV),
+ MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1);
+ BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
+ .addImm(0xBADC0FEE) // Misaligned load.
+ .addMemOperand(MMO);
+ MBB.erase(MI);
+ break;
+ }
+
case Hexagon::PS_tailcall_i:
MI.setDesc(get(Hexagon::J2_jump));
return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 5c709708f8f..9a7fda37cd4 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3081,7 +3081,7 @@ def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
def: Pat<(HexagonBARRIER), (Y2_barrier)>;
-def: Pat<(trap), (J2_trap0 (i32 0))>;
+def: Pat<(trap), (PS_crash)>;
// Read cycle counter.
def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td
index 50900d8cd25..7dd25d7d93d 100644
--- a/llvm/lib/Target/Hexagon/HexagonPseudo.td
+++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td
@@ -559,3 +559,8 @@ defm PS_storerh : NewCircularStore<IntRegs, HalfWordAccess>;
defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>;
defm PS_storeri : NewCircularStore<IntRegs, WordAccess>;
defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>;
+
+// A pseudo that generates a runtime crash. This is used to implement
+// __builtin_trap.
+let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1, isSolo = 1 in
+def PS_crash: InstHexagon<(outs), (ins), "", [], "", PSEUDO, TypePSEUDO>;
diff --git a/llvm/test/CodeGen/Hexagon/trap-crash.ll b/llvm/test/CodeGen/Hexagon/trap-crash.ll
new file mode 100644
index 00000000000..e940d98b620
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/trap-crash.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Generate code that is guaranteed to crash. At the moment, it's a
+; misaligned load.
+; CHECK: memd(##3134984174)
+
+target triple = "hexagon"
+
+; Function Attrs: noreturn nounwind
+define i32 @f0() #0 {
+entry:
+ tail call void @llvm.trap()
+ unreachable
+}
+
+; Function Attrs: cold noreturn nounwind
+declare void @llvm.trap() #1
+
+attributes #0 = { noreturn nounwind "target-cpu"="hexagonv60" }
+attributes #1 = { cold noreturn nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/trap-unreachable.ll b/llvm/test/CodeGen/Hexagon/trap-unreachable.ll
index 124b37a5c6c..b14f1e3c1a5 100644
--- a/llvm/test/CodeGen/Hexagon/trap-unreachable.ll
+++ b/llvm/test/CodeGen/Hexagon/trap-unreachable.ll
@@ -1,5 +1,7 @@
; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s
-; CHECK: trap
+
+; Trap is implemented via a misaligned load.
+; CHECK: memd(##3134984174)
define void @fred() #0 {
unreachable
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