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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-03-24 13:40:33 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-03-24 13:40:33 +0000 |
| commit | 5ebc92dbe164cfeb4eb5b5f5d4237175678191c1 (patch) | |
| tree | 7db6d83709ee57fc21a28bef8c7fcefb7f137654 | |
| parent | abb04956b6485fe3bd1f6e1e3020273095965ba2 (diff) | |
| download | bcm5719-llvm-5ebc92dbe164cfeb4eb5b5f5d4237175678191c1.tar.gz bcm5719-llvm-5ebc92dbe164cfeb4eb5b5f5d4237175678191c1.zip | |
[PowerPC] Disable direct moves for extractelement and bitcast in 32-bit mode
This patch corresponds to review:
http://reviews.llvm.org/D17711
It disables direct moves on these operations in 32-bit mode since the patterns
assume 64-bit registers. The final patch is slightly different from the
Phabricator review as the bitcast operations needed to be disabled in 32-bit
mode as well. This fixes PR26617.
llvm-svn: 264282
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr26617.ll | 15 |
2 files changed, 17 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 9d1eee0b9f5..70a22af9963 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -255,7 +255,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); - if (Subtarget.hasDirectMove()) { + if (Subtarget.hasDirectMove() && isPPC64) { setOperationAction(ISD::BITCAST, MVT::f32, Legal); setOperationAction(ISD::BITCAST, MVT::i32, Legal); setOperationAction(ISD::BITCAST, MVT::i64, Legal); @@ -557,7 +557,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); } - if (Subtarget.hasDirectMove()) { + if (Subtarget.hasDirectMove() && isPPC64) { setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); diff --git a/llvm/test/CodeGen/PowerPC/pr26617.ll b/llvm/test/CodeGen/PowerPC/pr26617.ll new file mode 100644 index 00000000000..474d7b94aaf --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr26617.ll @@ -0,0 +1,15 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s +define i32 @test(<4 x i32> %v, i32 %elem) #0 { +entry: + %vecext = extractelement <4 x i32> %v, i32 %elem + ret i32 %vecext +} +; CHECK: stxvw4x 34, +; CHECK: lwzx 3, + +define float @test2(i32 signext %a) { +entry: + %conv = bitcast i32 %a to float + ret float %conv +} +; CHECK-NOT: mtvsr |
