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| author | Craig Topper <craig.topper@gmail.com> | 2016-04-15 04:57:09 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-04-15 04:57:09 +0000 |
| commit | 5e20fd3e7c9f83f62b825cce43375605b36de186 (patch) | |
| tree | 04325624f81d7045080047086f15067b949a43e9 | |
| parent | 90fb2baff7f48ac1525ff09c44874dd876d6cd63 (diff) | |
| download | bcm5719-llvm-5e20fd3e7c9f83f62b825cce43375605b36de186.tar.gz bcm5719-llvm-5e20fd3e7c9f83f62b825cce43375605b36de186.zip | |
[X86] Combine an if and else block that had the same set of calls to setOperationAction that only varied in Legal/Custom. Use the ternary operator on that argument instead. NFC
llvm-svn: 266410
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 71 |
1 files changed, 24 insertions, 47 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index fcd7f0777f9..eb9e31c8e5e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1113,32 +1113,34 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FMA, VT, Legal); } - if (Subtarget.hasInt256()) { - for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { - setOperationAction(ISD::ADD, VT, Legal); - setOperationAction(ISD::SUB, VT, Legal); - } + bool HasInt256 = Subtarget.hasInt256(); + + for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { + setOperationAction(ISD::ADD, VT, HasInt256 ? Legal : Custom); + setOperationAction(ISD::SUB, VT, HasInt256 ? Legal : Custom); + } - setOperationAction(ISD::MUL, MVT::v4i64, Custom); - setOperationAction(ISD::MUL, MVT::v8i32, Legal); - setOperationAction(ISD::MUL, MVT::v16i16, Legal); - setOperationAction(ISD::MUL, MVT::v32i8, Custom); + setOperationAction(ISD::MUL, MVT::v4i64, Custom); + setOperationAction(ISD::MUL, MVT::v8i32, HasInt256 ? Legal : Custom); + setOperationAction(ISD::MUL, MVT::v16i16, HasInt256 ? Legal : Custom); + setOperationAction(ISD::MUL, MVT::v32i8, Custom); - setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom); - setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom); + setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom); + setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom); - setOperationAction(ISD::MULHU, MVT::v16i16, Legal); - setOperationAction(ISD::MULHS, MVT::v16i16, Legal); - setOperationAction(ISD::MULHU, MVT::v32i8, Custom); - setOperationAction(ISD::MULHS, MVT::v32i8, Custom); + setOperationAction(ISD::MULHU, MVT::v16i16, HasInt256 ? Legal : Custom); + setOperationAction(ISD::MULHS, MVT::v16i16, HasInt256 ? Legal : Custom); + setOperationAction(ISD::MULHU, MVT::v32i8, Custom); + setOperationAction(ISD::MULHS, MVT::v32i8, Custom); - for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { - setOperationAction(ISD::SMAX, VT, Legal); - setOperationAction(ISD::UMAX, VT, Legal); - setOperationAction(ISD::SMIN, VT, Legal); - setOperationAction(ISD::UMIN, VT, Legal); - } + for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { + setOperationAction(ISD::SMAX, VT, HasInt256 ? Legal : Custom); + setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom); + setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom); + setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom); + } + if (HasInt256) { setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i64, Custom); setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i32, Custom); setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v16i16, Custom); @@ -1161,31 +1163,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal); setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal); setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal); - } else { - for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { - setOperationAction(ISD::ADD, VT, Custom); - setOperationAction(ISD::SUB, VT, Custom); - } - - setOperationAction(ISD::MUL, MVT::v4i64, Custom); - setOperationAction(ISD::MUL, MVT::v8i32, Custom); - setOperationAction(ISD::MUL, MVT::v16i16, Custom); - setOperationAction(ISD::MUL, MVT::v32i8, Custom); - - setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom); - setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom); - - setOperationAction(ISD::MULHU, MVT::v16i16, Custom); - setOperationAction(ISD::MULHS, MVT::v16i16, Custom); - setOperationAction(ISD::MULHU, MVT::v32i8, Custom); - setOperationAction(ISD::MULHS, MVT::v32i8, Custom); - - for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { - setOperationAction(ISD::SMAX, VT, Custom); - setOperationAction(ISD::UMAX, VT, Custom); - setOperationAction(ISD::SMIN, VT, Custom); - setOperationAction(ISD::UMIN, VT, Custom); - } } // In the customized shift lowering, the legal cases in AVX2 will be @@ -1221,7 +1198,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); } - if (Subtarget.hasInt256()) + if (HasInt256) setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. |
