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| author | vhscampos <Victor.Campos@arm.com> | 2019-10-22 11:43:51 +0100 |
|---|---|---|
| committer | vhscampos <Victor.Campos@arm.com> | 2019-10-28 10:59:18 +0000 |
| commit | 5d35b7d9e1a34b45c19609f754050e4263bee4ce (patch) | |
| tree | c8a356262350c8f3818df9495af871f44b77f722 | |
| parent | da720a38b9f24cc92b46fd5df503b13d5c823285 (diff) | |
| download | bcm5719-llvm-5d35b7d9e1a34b45c19609f754050e4263bee4ce.tar.gz bcm5719-llvm-5d35b7d9e1a34b45c19609f754050e4263bee4ce.zip | |
[ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64
Summary:
Adding support for ACLE intrinsics.
Patch by Michael Platings.
Reviewers: chill, t.p.northover, efriedma
Reviewed By: chill
Subscribers: kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69297
| -rw-r--r-- | clang/lib/Headers/arm_acle.h | 4 | ||||
| -rw-r--r-- | clang/test/CodeGen/arm_acle.c | 49 |
2 files changed, 53 insertions, 0 deletions
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h index 0510e6fd809..942172f9f8e 100644 --- a/clang/lib/Headers/arm_acle.h +++ b/clang/lib/Headers/arm_acle.h @@ -609,9 +609,13 @@ __jcvt(double __a) { #define __arm_rsr(sysreg) __builtin_arm_rsr(sysreg) #define __arm_rsr64(sysreg) __builtin_arm_rsr64(sysreg) #define __arm_rsrp(sysreg) __builtin_arm_rsrp(sysreg) +#define __arm_rsrf(sysreg) __builtin_bit_cast(float, __arm_rsr(sysreg)) +#define __arm_rsrf64(sysreg) __builtin_bit_cast(double, __arm_rsr64(sysreg)) #define __arm_wsr(sysreg, v) __builtin_arm_wsr(sysreg, v) #define __arm_wsr64(sysreg, v) __builtin_arm_wsr64(sysreg, v) #define __arm_wsrp(sysreg, v) __builtin_arm_wsrp(sysreg, v) +#define __arm_wsrf(sysreg, v) __arm_wsr(sysreg, __builtin_bit_cast(uint32_t, v)) +#define __arm_wsrf64(sysreg, v) __arm_wsr64(sysreg, __builtin_bit_cast(uint64_t, v)) /* Memory Tagging Extensions (MTE) Intrinsics */ #if __ARM_FEATURE_MEMORY_TAGGING diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c index ce2c5fac70b..7463d0d8e1d 100644 --- a/clang/test/CodeGen/arm_acle.c +++ b/clang/test/CodeGen/arm_acle.c @@ -822,6 +822,55 @@ void test_wsrp(void *v) { __arm_wsrp("sysreg", v); } +// ARM-LABEL: test_rsrf +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]]) +// ARM-NOT: uitofp +// ARM: bitcast +float test_rsrf() { +#ifdef __ARM_32BIT_STATE + return __arm_rsrf("cp1:2:c3:c4:5"); +#else + return __arm_rsrf("1:2:3:4:5"); +#endif +} +// ARM-LABEL: test_rsrf64 +// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]]) +// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]]) +// ARM-NOT: uitofp +// ARM: bitcast +double test_rsrf64() { +#ifdef __ARM_32BIT_STATE + return __arm_rsrf64("cp1:2:c3"); +#else + return __arm_rsrf64("1:2:3:4:5"); +#endif +} +// ARM-LABEL: test_wsrf +// ARM-NOT: fptoui +// ARM: bitcast +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}}) +void test_wsrf(float v) { +#ifdef __ARM_32BIT_STATE + __arm_wsrf("cp1:2:c3:c4:5", v); +#else + __arm_wsrf("1:2:3:4:5", v); +#endif +} +// ARM-LABEL: test_wsrf64 +// ARM-NOT: fptoui +// ARM: bitcast +// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}}) +// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}}) +void test_wsrf64(double v) { +#ifdef __ARM_32BIT_STATE + __arm_wsrf64("cp1:2:c3", v); +#else + __arm_wsrf64("1:2:3:4:5", v); +#endif +} + // AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"} // AArch32: ![[M3]] = !{!"cp1:2:c3"} // AArch32: ![[M4]] = !{!"sysreg"} |
