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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-13 19:58:27 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-13 19:58:27 +0000 |
| commit | 5d26d0435713245fbd3f265148662589688ed0da (patch) | |
| tree | ad6c531ca6ebd7051530a663ab7f254d0587681c | |
| parent | 377a620f9842fa2b84053b7a24e2e0cb54c5b2d5 (diff) | |
| download | bcm5719-llvm-5d26d0435713245fbd3f265148662589688ed0da.tar.gz bcm5719-llvm-5d26d0435713245fbd3f265148662589688ed0da.zip | |
Fix typo
llvm-svn: 217730
| -rw-r--r-- | llvm/lib/Target/R600/SIShrinkInstructions.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/SIShrinkInstructions.cpp b/llvm/lib/Target/R600/SIShrinkInstructions.cpp index caf2572c11b..c33514f719f 100644 --- a/llvm/lib/Target/R600/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/R600/SIShrinkInstructions.cpp @@ -213,10 +213,10 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { unsigned DstReg = MI.getOperand(0).getReg(); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { // VOPC instructions can only write to the VCC register. We can't - // force them to use VCC here, because the register allocator - // has trouble with sequences like this, which cause the allocator - // to run out of registes if vreg0 and vreg1 belong to the VCCReg - // register class: + // force them to use VCC here, because the register allocator has + // trouble with sequences like this, which cause the allocator to run + // out of registers if vreg0 and vreg1 belong to the VCCReg register + // class: // vreg0 = VOPC; // vreg1 = VOPC; // S_AND_B64 vreg0, vreg1 |

