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authorSanjay Patel <spatel@rotateright.com>2015-07-30 00:04:21 +0000
committerSanjay Patel <spatel@rotateright.com>2015-07-30 00:04:21 +0000
commit5bfbb36a09fac45bd0230fceb42a58e3c1977620 (patch)
tree6a216a0d6c5b47ec2156bdbc1276f7db37ae7cf3
parentc69bf1b4c02a4e6a3ce93ca8c9bfc11567c42d8a (diff)
downloadbcm5719-llvm-5bfbb36a09fac45bd0230fceb42a58e3c1977620.tar.gz
bcm5719-llvm-5bfbb36a09fac45bd0230fceb42a58e3c1977620.zip
push fast-math check for machine-combiner reassociations into instruction-type check; NFC
This makes it simpler to add instruction types that don't depend on fast-math. llvm-svn: 243596
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp11
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 98697e834e4..010c2b874c7 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -6348,8 +6348,8 @@ static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
// TODO: There are many more machine instruction opcodes to match:
// 1. Other data types (integer, vectors)
// 2. Other math / logic operations (and, or)
-static bool isAssociativeAndCommutative(unsigned Opcode) {
- switch (Opcode) {
+static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
+ switch (Inst.getOpcode()) {
case X86::ADDSDrr:
case X86::ADDSSrr:
case X86::VADDSDrr:
@@ -6358,7 +6358,7 @@ static bool isAssociativeAndCommutative(unsigned Opcode) {
case X86::MULSSrr:
case X86::VMULSDrr:
case X86::VMULSSrr:
- return true;
+ return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
default:
return false;
}
@@ -6374,7 +6374,7 @@ static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
// 2. The instruction must have virtual register definitions for its
// operands in the same basic block.
// 3. The instruction must have a reassociable sibling.
- if (isAssociativeAndCommutative(Inst.getOpcode()) &&
+ if (isAssociativeAndCommutative(Inst) &&
hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
hasReassocSibling(Inst, Commuted))
return true;
@@ -6391,9 +6391,6 @@ static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
// that pattern.
bool X86InstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
- if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
- return false;
-
// TODO: There is nothing x86-specific here except the instruction type.
// This logic could be hoisted into the machine combiner pass itself.
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